| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_lowering_gm107.cpp | 95 case OP_QUADON:
142 bld.mkOp(OP_QUADON, TYPE_U32, bar);
|
| H A D | nv50_ir_target_gm107.cpp | 262 case OP_QUADON:
|
| H A D | nv50_ir_target_nv50.cpp | 129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
134 OP_CALL, OP_PREBREAK, OP_PRERET, OP_QUADON, OP_QUADPOP, OP_JOINAT,
|
| H A D | nv50_ir_build_util.h | 272 op == OP_QUADON || op == OP_QUADPOP ||
|
| H A D | nv50_ir_target_nvc0.cpp | 212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
218 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
|
| H A D | nv50_ir_lowering_gv100.cpp | 294 case OP_QUADON:
|
| H A D | nv50_ir.h | 151 OP_QUADON, enumerator in enum:nv50_ir::operation
|
| H A D | nv50_ir_emit_gk110.cpp | 1535 case OP_QUADON: code[1] = 0x1b800000; mask = 0; break;
2687 case OP_QUADON:
|
| H A D | nv50_ir_emit_nv50.cpp | 2099 case OP_QUADON:
2239 insn->op == OP_QUADON ||
|
| H A D | nv50_ir_emit_gm107.cpp | 3465 case OP_QUADON:
4004 if (insn->op == OP_QUADON ||
|
| H A D | nv50_ir_emit_nvc0.cpp | 1482 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
2881 case OP_QUADON:
|
| H A D | nv50_ir_lowering_nv50.cpp | 1014 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
|
| H A D | nv50_ir_lowering_nvc0.cpp | 1228 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 262 case OP_QUADON:
|
| H A D | nv50_ir_target_nv50.cpp | 129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
134 OP_CALL, OP_PREBREAK, OP_PRERET, OP_QUADON, OP_QUADPOP, OP_JOINAT,
|
| H A D | nv50_ir_build_util.h | 266 op == OP_QUADON || op == OP_QUADPOP ||
|
| H A D | nv50_ir_lowering_gm107.cpp | 123 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
|
| H A D | nv50_ir_target_nvc0.cpp | 212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
218 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
|
| H A D | nv50_ir.h | 148 OP_QUADON, enumerator in enum:nv50_ir::operation
|
| H A D | nv50_ir_emit_gk110.cpp | 1528 case OP_QUADON: code[1] = 0x1b800000; mask = 0; break;
2680 case OP_QUADON:
|
| H A D | nv50_ir_emit_nv50.cpp | 2012 case OP_QUADON:
2152 insn->op == OP_QUADON ||
|
| H A D | nv50_ir_lowering_nv50.cpp | 960 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
|
| H A D | nv50_ir_emit_gm107.cpp | 3400 case OP_QUADON:
4081 if (insn->op == OP_QUADON ||
|
| H A D | nv50_ir_emit_nvc0.cpp | 1475 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break;
2874 case OP_QUADON:
|
| H A D | nv50_ir_lowering_nvc0.cpp | 1214 bld.mkOp(OP_QUADON, TYPE_NONE, NULL);
|