Searched refs:OP_TXD (Results 1 - 24 of 24) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_emit_gk110.cpp1275 case OP_TXD:
1293 case OP_TXD:
1332 case OP_TXD: break;
1347 if (i->op != OP_TXD && i->tex.derivAll)
1379 case OP_TXD: code[1] |= 0x00400000; break;
2653 case OP_TXD:
H A Dnv50_ir_lowering_nvc0.cpp1016 if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) {
1026 i->op == OP_TXD || chipset < NVISA_GM107_CHIPSET)) {
1107 if (i->op != OP_TXD || chipset < NVISA_GK104_CHIPSET) {
1144 if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
3098 case OP_TXD:
H A Dnv50_ir_lowering_nv50.cpp730 if (i->tex.target.isCube() && i->op != OP_TXD) {
1405 case OP_TXD:
H A Dnv50_ir.h124 OP_TXD, // texture derivatives enumerator in enum:nv50_ir::operation
H A Dnv50_ir.cpp938 if (op == OP_TXD) {
H A Dnv50_ir_emit_nvc0.cpp1333 case OP_TXD: code[1] = 0xe0000000; break;
1346 if (i->op != OP_TXD && i->tex.derivAll)
2823 case OP_TXD:
H A Dnv50_ir_ra.cpp1134 case OP_TXD:
2337 if (tex->op == OP_TXD) {
2416 if (tex->op == OP_TXD && tex->tex.useOffsets)
H A Dnv50_ir_emit_nv50.cpp2050 case OP_TXD:
H A Dnv50_ir_emit_gm107.cpp3641 case OP_TXD:
H A Dnv50_ir_from_nir.cpp480 return OP_TXD;
H A Dnv50_ir_from_tgsi.cpp2368 if (texi->op == OP_TXD) {
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_emit_gk110.cpp1282 case OP_TXD:
1300 case OP_TXD:
1339 case OP_TXD: break;
1354 if (i->op != OP_TXD && i->tex.derivAll)
1386 case OP_TXD: code[1] |= 0x00400000; break;
2660 case OP_TXD:
H A Dnv50_ir.h127 OP_TXD, // texture derivatives enumerator in enum:nv50_ir::operation
H A Dnv50_ir_target_gv100.cpp395 case OP_TXD: return &opInfo_TXD;
H A Dnv50_ir_lowering_nvc0.cpp1030 if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) {
1040 i->op == OP_TXD || chipset < NVISA_GM107_CHIPSET)) {
1121 if (i->op != OP_TXD || chipset < NVISA_GK104_CHIPSET) {
1158 if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
3312 case OP_TXD:
H A Dnv50_ir.cpp940 if (op == OP_TXD) {
H A Dnv50_ir_emit_nvc0.cpp1340 case OP_TXD: code[1] = 0xe0000000; break;
1353 if (i->op != OP_TXD && i->tex.derivAll)
2830 case OP_TXD:
H A Dnv50_ir_ra.cpp1181 case OP_TXD:
2399 if (tex->op == OP_TXD) {
2478 if (tex->op == OP_TXD && tex->tex.useOffsets)
H A Dnv50_ir_emit_gv100.cpp1990 case OP_TXD:
H A Dnv50_ir_lowering_nv50.cpp784 if (i->tex.target.isCube() && i->op != OP_TXD) {
2202 case OP_TXD:
H A Dnv50_ir_emit_nv50.cpp2137 case OP_TXD:
H A Dnv50_ir_emit_gm107.cpp3714 case OP_TXD:
H A Dnv50_ir_from_nir.cpp512 return OP_TXD;
H A Dnv50_ir_from_tgsi.cpp2356 if (texi->op == OP_TXD) {

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