Searched refs:Opcode (Results 1 - 25 of 224) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c35 .Opcode = RC_OPCODE_NOP,
39 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
43 .Opcode = RC_OPCODE_ABS,
50 .Opcode = RC_OPCODE_ADD,
57 .Opcode = RC_OPCODE_ARL,
63 .Opcode = RC_OPCODE_ARR,
69 .Opcode = RC_OPCODE_CEIL,
76 .Opcode = RC_OPCODE_CLAMP,
83 .Opcode = RC_OPCODE_CMP,
90 .Opcode
[all...]
H A Dradeon_emulate_loops.c98 switch(inst->U.I.Opcode){
136 opcode = rc_get_opcode_info(inst->U.I.Opcode);
166 switch(inst->U.I.Opcode){
238 switch(inst->U.I.Opcode){
286 switch(loop->Cond->U.I.Opcode){
332 if(inst->U.I.Opcode != RC_OPCODE_BGNLOOP){
349 switch(ptr->U.I.Opcode){
356 if (ptr->U.I.Opcode == RC_OPCODE_BGNLOOP) {
358 } else if (ptr->U.I.Opcode == RC_OPCODE_ENDLOOP) {
374 if(ptr->Next->U.I.Opcode !
[all...]
H A Dradeon_pair_translate.c42 switch(inst->Opcode) {
48 inst->Opcode = RC_OPCODE_MAD;
70 inst->Opcode = RC_OPCODE_MAD;
75 inst->Opcode = RC_OPCODE_MAD;
99 switch(inst->Opcode) {
163 pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
165 pair->RGB.Opcode = inst->Opcode;
170 pair->Alpha.Opcode = inst->Opcode;
[all...]
H A Dradeon_optimize.c73 reader_data->Writer->U.I.PreSub.Opcode,
93 (inst->U.I.Opcode == RC_OPCODE_TEX ||
94 inst->U.I.Opcode == RC_OPCODE_TXB ||
95 inst->U.I.Opcode == RC_OPCODE_TXP ||
96 inst->U.I.Opcode == RC_OPCODE_TXD ||
97 inst->U.I.Opcode == RC_OPCODE_TXL ||
98 inst->U.I.Opcode == RC_OPCODE_KIL)){
165 if (inst->U.I.Opcode != RC_OPCODE_MOV ||
234 inst->U.I.Opcode = RC_OPCODE_MUL;
241 inst->U.I.Opcode
[all...]
H A Dradeon_vert_fc.c129 new_inst->U.I.Opcode = RC_ME_PRED_SEQ;
149 new_inst->U.I.Opcode = RC_OPCODE_ADD;
163 inst->U.I.Opcode = RC_OPCODE_RCP;
169 inst->U.I.Opcode = RC_ME_PRED_SET_CLR;
183 new_inst->U.I.Opcode = RC_ME_PRED_SET_RESTORE;
206 if (inst->Next->U.I.Opcode == RC_OPCODE_BRK) {
212 inst->U.I.Opcode = RC_ME_PRED_SEQ;
215 inst->U.I.Opcode = RC_ME_PRED_SNEQ;
219 inst->U.I.Opcode = RC_VE_PRED_SNEQ_PUSH;
245 switch (inst->U.I.Opcode) {
[all...]
H A Dradeon_program_tex.c67 inst_mov->U.I.Opcode = RC_OPCODE_MUL;
89 inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL;
109 inst->U.I.Opcode = RC_OPCODE_TEX;
133 if (inst->U.I.Opcode != RC_OPCODE_TEX &&
134 inst->U.I.Opcode != RC_OPCODE_TXB &&
135 inst->U.I.Opcode != RC_OPCODE_TXP &&
136 inst->U.I.Opcode != RC_OPCODE_TXD &&
137 inst->U.I.Opcode != RC_OPCODE_TXL &&
138 inst->U.I.Opcode !
[all...]
H A Dradeon_opcodes.h247 rc_opcode Opcode; member in struct:rc_opcode_info
276 assert(rc_opcodes[opcode].Opcode == opcode);
H A Dradeon_program.h65 rc_presubtract_op Opcode; member in struct:rc_presub_instruction
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8; member in struct:rc_sub_instruction
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c37 .Opcode = RC_OPCODE_NOP,
41 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
45 .Opcode = RC_OPCODE_ABS,
52 .Opcode = RC_OPCODE_ADD,
59 .Opcode = RC_OPCODE_ARL,
65 .Opcode = RC_OPCODE_ARR,
71 .Opcode = RC_OPCODE_CEIL,
78 .Opcode = RC_OPCODE_CLAMP,
85 .Opcode = RC_OPCODE_CMP,
92 .Opcode
[all...]
H A Dradeon_emulate_loops.c98 switch(inst->U.I.Opcode){
136 opcode = rc_get_opcode_info(inst->U.I.Opcode);
166 switch(inst->U.I.Opcode){
238 switch(inst->U.I.Opcode){
286 switch(loop->Cond->U.I.Opcode){
332 if(inst->U.I.Opcode != RC_OPCODE_BGNLOOP){
349 switch(ptr->U.I.Opcode){
356 if (ptr->U.I.Opcode == RC_OPCODE_BGNLOOP) {
358 } else if (ptr->U.I.Opcode == RC_OPCODE_ENDLOOP) {
374 if(ptr->Next->U.I.Opcode !
[all...]
H A Dradeon_pair_translate.c44 switch(inst->Opcode) {
50 inst->Opcode = RC_OPCODE_MAD;
72 inst->Opcode = RC_OPCODE_MAD;
77 inst->Opcode = RC_OPCODE_MAD;
101 switch(inst->Opcode) {
165 pair->RGB.Opcode = RC_OPCODE_REPL_ALPHA;
167 pair->RGB.Opcode = inst->Opcode;
172 pair->Alpha.Opcode = inst->Opcode;
[all...]
H A Dradeon_optimize.c75 reader_data->Writer->U.I.PreSub.Opcode,
95 (inst->U.I.Opcode == RC_OPCODE_TEX ||
96 inst->U.I.Opcode == RC_OPCODE_TXB ||
97 inst->U.I.Opcode == RC_OPCODE_TXP ||
98 inst->U.I.Opcode == RC_OPCODE_TXD ||
99 inst->U.I.Opcode == RC_OPCODE_TXL ||
100 inst->U.I.Opcode == RC_OPCODE_KIL)){
167 if (inst->U.I.Opcode != RC_OPCODE_MOV ||
236 inst->U.I.Opcode = RC_OPCODE_MUL;
243 inst->U.I.Opcode
[all...]
H A Dradeon_vert_fc.c129 new_inst->U.I.Opcode = RC_ME_PRED_SEQ;
149 new_inst->U.I.Opcode = RC_OPCODE_ADD;
163 inst->U.I.Opcode = RC_OPCODE_RCP;
169 inst->U.I.Opcode = RC_ME_PRED_SET_CLR;
183 new_inst->U.I.Opcode = RC_ME_PRED_SET_RESTORE;
206 if (inst->Next->U.I.Opcode == RC_OPCODE_BRK) {
212 inst->U.I.Opcode = RC_ME_PRED_SEQ;
215 inst->U.I.Opcode = RC_ME_PRED_SNEQ;
219 inst->U.I.Opcode = RC_VE_PRED_SNEQ_PUSH;
245 switch (inst->U.I.Opcode) {
[all...]
H A Dradeon_program_tex.c67 inst_mov->U.I.Opcode = RC_OPCODE_MUL;
89 inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL;
109 inst->U.I.Opcode = RC_OPCODE_TEX;
133 if (inst->U.I.Opcode != RC_OPCODE_TEX &&
134 inst->U.I.Opcode != RC_OPCODE_TXB &&
135 inst->U.I.Opcode != RC_OPCODE_TXP &&
136 inst->U.I.Opcode != RC_OPCODE_TXD &&
137 inst->U.I.Opcode != RC_OPCODE_TXL &&
138 inst->U.I.Opcode !
[all...]
H A Dradeon_opcodes.h247 rc_opcode Opcode; member in struct:rc_opcode_info
276 assert(rc_opcodes[opcode].Opcode == opcode);
H A Dradeon_program.h65 rc_presubtract_op Opcode; member in struct:rc_presub_instruction
82 * Opcode of this instruction, according to \ref rc_opcode enums.
84 unsigned int Opcode:8; member in struct:rc_sub_instruction
/xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/includes/
H A DDecoder.h93 #define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE))
94 #define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE))
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c120 switch (inst->Instruction.Opcode) {
266 if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ)
274 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
275 inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
276 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
277 inst->Instruction.Opcode == TGSI_OPCODE_TXP)
282 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
284 else if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
285 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
286 inst->Instruction.Opcode
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c181 switch (inst->Instruction.Opcode) {
327 if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ)
335 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
336 inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
337 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
338 inst->Instruction.Opcode == TGSI_OPCODE_TXP)
343 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
345 else if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
346 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
347 inst->Instruction.Opcode
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
H A Dsfn_instruction_tex.h36 enum Opcode { enum in class:r600::TexInstruction
75 TexInstruction(Opcode op, const GPRVector& dest, const GPRVector& src, unsigned sid,
123 static const char *opname(Opcode code);
125 Opcode m_opcode;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/program/
H A Dprog_opt_constant_fold.c134 switch (inst->Opcode) {
149 inst->Opcode = OPCODE_MOV;
179 inst->Opcode = OPCODE_MOV;
204 if (inst->Opcode >= OPCODE_DP3)
207 if (inst->Opcode == OPCODE_DP4)
210 inst->Opcode = OPCODE_MOV;
234 inst->Opcode = OPCODE_MOV;
258 inst->Opcode = OPCODE_MOV;
266 inst->Opcode = OPCODE_MOV;
290 inst->Opcode
[all...]
H A Dprog_instruction.c82 enum prog_opcode Opcode; member in struct:instruction_info
90 * \note Opcode should equal array index!
163 assert(opcode == InstInfo[opcode].Opcode);
164 assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
176 assert(opcode == InstInfo[opcode].Opcode);
177 assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
/xsrc/external/mit/MesaLib/dist/src/mesa/program/
H A Dprog_opt_constant_fold.c134 switch (inst->Opcode) {
149 inst->Opcode = OPCODE_MOV;
179 inst->Opcode = OPCODE_MOV;
204 if (inst->Opcode >= OPCODE_DP3)
207 if (inst->Opcode == OPCODE_DP4)
210 inst->Opcode = OPCODE_MOV;
234 inst->Opcode = OPCODE_MOV;
258 inst->Opcode = OPCODE_MOV;
266 inst->Opcode = OPCODE_MOV;
290 inst->Opcode
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_reg.h64 #define BRW_3D(Pipeline,Opcode,Subopcode) \
67 ((Opcode) << 24) | \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_reg.h64 #define BRW_3D(Pipeline,Opcode,Subopcode) \
67 ((Opcode) << 24) | \

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