Searched refs:R200_PP_TXCBLEND2_0 (Results 1 - 13 of 13) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 174 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
197 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
229 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
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| H A D | r200_sanity.c | 459 { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
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| H A D | r200_reg.h | 1231 #define R200_PP_TXCBLEND2_0 0x2f04 macro
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 161 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
187 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
219 OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 |
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| H A D | r200_sanity.c | 459 { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
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| H A D | r200_reg.h | 1231 #define R200_PP_TXCBLEND2_0 0x2f04 macro
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| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | radeon_render.c | 880 OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
930 OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0);
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| H A D | radeon_textured_videofuncs.c | 805 OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
906 OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
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| H A D | radeon_exa_render.c | 1116 OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
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| H A D | radeon_reg.h | 2877 #define R200_PP_TXCBLEND2_0 0x2f04 macro
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| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 632 OUT_RING_REG(R200_PP_TXCBLEND2_0,
733 OUT_RING_REG(R200_PP_TXCBLEND2_0,
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| H A D | radeon_exa_render.c | 1056 OUT_RING_REG(R200_PP_TXCBLEND2_0,
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| H A D | radeon_reg.h | 2877 #define R200_PP_TXCBLEND2_0 0x2f04 macro
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