Searched refs:R200_PP_TXOFFSET_0 (Results 1 - 17 of 17) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 304 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
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| H A D | r200_sanity.c | 109 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
413 { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
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| H A D | r200_state_init.c | 107 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
582 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
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| H A D | r200_reg.h | 1077 #define R200_PP_TXOFFSET_0 0x2d00 macro
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| H A D | r200_blit.c | 294 OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1);
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| H A D | r200_sanity.c | 109 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
413 { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
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| H A D | r200_state_init.c | 107 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
582 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0));
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| H A D | r200_reg.h | 1077 #define R200_PP_TXOFFSET_0 0x2d00 macro
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| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| H A D | radeon_render.c | 825 OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation +
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| H A D | radeon_textured_videofuncs.c | 741 OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
897 OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, txoffset, src_bo);
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| H A D | radeon_exa_render.c | 893 EMIT_READ_OFFSET(R200_PP_TXOFFSET_0, txoffset, pPix);
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| H A D | radeon_reg.h | 2754 #define R200_PP_TXOFFSET_0 0x2d00 macro
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 102 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 101 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
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| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| H A D | radeon_textured_videofuncs.c | 568 OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, 0, src_bo);
724 OUT_TEXTURE_REG(R200_PP_TXOFFSET_0, 0, src_bo);
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| H A D | radeon_exa_render.c | 838 EMIT_READ_OFFSET(R200_PP_TXOFFSET_0, txoffset, pPix);
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| H A D | radeon_reg.h | 2754 #define R200_PP_TXOFFSET_0 0x2d00 macro
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