Searched refs:RA (Results 1 - 25 of 27) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/tests/
H A Dst_tests_common.h40 struct RA {}; struct
57 const std::vector<std::tuple<int,int,int>>&_to, RA with_reladdr);
H A Dtest_glsl_to_tgsi_lifetime.cpp1634 { TGSI_OPCODE_MOV, {MT(3,0,0)}, {MT(2,1,0)}, {}, RA()},
1647 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(4,0,1)}, {}, RA()},
1660 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(in2,0,0)}, {MT(5,1,0)}, RA()},
1673 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(in2,0,0)}, {MT(2,0,1)}, RA()},
1686 { TGSI_OPCODE_MOV , {MT(5,1,0)}, {MT(in1,0,0)}, {}, RA()},
1698 { TGSI_OPCODE_MOV , {MT(5,0,1)}, {MT(in1,0,0)}, {}, RA()},
H A Dst_tests_common.cpp91 const vector<tuple<int,int,int>>&_to, RA with_reladdr):
/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/tests/
H A Dst_tests_common.h40 struct RA {}; struct
57 const std::vector<std::tuple<int,int,int>>&_to, RA with_reladdr);
H A Dtest_glsl_to_tgsi_lifetime.cpp1634 { TGSI_OPCODE_MOV, {MT(3,0,0)}, {MT(2,1,0)}, {}, RA()},
1647 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(4,0,1)}, {}, RA()},
1660 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(in2,0,0)}, {MT(5,1,0)}, RA()},
1673 { TGSI_OPCODE_MOV , {MT(3,0,0)}, {MT(in2,0,0)}, {MT(2,0,1)}, RA()},
1686 { TGSI_OPCODE_MOV , {MT(5,1,0)}, {MT(in1,0,0)}, {}, RA()},
1698 { TGSI_OPCODE_MOV , {MT(5,0,1)}, {MT(in1,0,0)}, {}, RA()},
H A Dst_tests_common.cpp91 const vector<tuple<int,int,int>>&_to, RA with_reladdr):
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.0.5.rst78 - intel/fs/ra: Stop adding RA interference to too many SENDS nodes
H A D20.1.5.rst61 - aco: prevent infinite recursion in RA for subdword variables
H A D20.1.8.rst125 - aco: Fix integer overflows when emitting parallel copies during RA
H A D11.1.2.rst117 - nv50/ir: fix memory corruption when spilling and redoing RA
H A D10.3.3.rst126 - freedreno/ir3: fix potential segfault in RA
H A D19.3.3.rst105 - intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT
H A D20.1.0.rst492 - pan/midgard: Remove incorrect comment in RA
730 - pan/bi: Fix RA wrt 16-bit swizzles
1201 - aco: validate RA of subdword assignments
1203 - aco: fix Temp and assignment of renamed operands during RA
1209 - aco: align subdword registers during RA when necessary
1231 - aco: during RA only insert into renames table if a variable got
1234 - aco: refactor try_remove_trivial_phi() in RA
1239 - aco: RA - move all std::function objects into proper functions
1252 - aco: simplify operand handling in RA
1255 - aco: create pseudo dummy instruction in RA t
[all...]
H A D19.3.0.rst311 - pan/midgard: Fix corner case in RA
328 - pan/midgard: Fix misc. RA issues
330 - pan/midgard: Handle fragment writeout in RA
331 - pan/midgard: Schedule before RA
378 - pan/midgard: Move RA's liveness analysis into midgard_liveness.c
404 - pan/midgard: Handle nontrivial masks in texture RA
828 - aco: preserve kill flag on moved operands during RA
2180 - freedreno/ir3: Extend RA with mechanism for pre-coloring registers
H A D21.2.0.rst729 - pan/bi: Bundle after RA
730 - pan/bi: Add post-RA optimizer
733 - pan/bi: Use explicit affinities in RA
734 - pan/bi: Inline spilling in RA
746 - pan/bi: Track words instead of bytes in RA
932 - pan/bi: Only spill nodes that could progress in RA
1451 - ir3/delay: Delete pre-RA repeat handling
2029 - vc4: Use the ra_alloc_contig_reg_class() function to speed up RA.
2030 - v3d: Use the ra_alloc_contig_reg_class() function to speed up RA.
2031 - intel/fs: Use ra_alloc_contig_reg_class() to speed up RA
[all...]
H A D21.3.0.rst286 - agx: Drop dated /* TODO: RA \*/
888 - ir3: Document RA-related register flags better
911 - ir3: Fix RA debug printing
3554 - aco: combine DPP into VALU before RA
3555 - aco: combine DPP into VALU after RA
3556 - aco/tests: add tests for pre-RA DPP combining
3557 - aco/tests: add tests for post-RA DPP combining
H A D20.2.0.rst406 - pan/mdg: Respect !32-bit sizes in RA
424 - pan/mdg: Set RA bounds for fp16
433 - pan/mdg: Use shifts instead of division for RA sizes
639 - pan/mdg: Analyze types for 64-bitness in RA
1039 - intel/fs: Remove min_dispatch_width spilling decision from RA
1282 - aco: prevent infinite recursion in RA for subdword variables
3656 - v3d: Retry with the fallback scheduler when RA fails
4075 - freedreno/ir3: remove RA "q-values" optimization
4698 - aco: Fix integer overflows when emitting parallel copies during RA
H A D21.0.0.rst295 - pan/bi: Fix off-by-one in RA
341 - pan/bi: Remove reference to 64-bit RA
419 - pan/mdg: Fix bound setting in RA for sources
445 - pan/bi: Fix RA of node 0
836 - aco/RA: fix subdword operands on VOP3P instructions
1573 - pan/bi: Iterate from zero when setting RA interference
H A D19.1.0.rst521 - panfrost: Respect backwards branches in RA
568 - panfrost/midgard: Fix RA when temp_count = 0
1418 - v3d: Include a count of register pressure in the RA failure dumps.
1425 - vc4: Switch the post-RA scheduler over to the DAG datastructure.
2276 - intel/fs/ra: Stop adding RA interference to too many SENDS nodes
H A D21.1.0.rst378 - pan/bi: Fix RA of node 0
403 - pan/bi: Permit multiple destinations in RA
621 - pan/bi: Fix RA of node 0 again
694 - pan/bi: Remove TODO: RA warnings
1344 - aco/RA: fix subdword operands on VOP3P instructions
2432 - pan/bi: Iterate from zero when setting RA interference
4835 - aco: don't update register demand during RA validation
H A D20.0.0.rst720 - aco: preserve kill flag on moved operands during RA
1292 - intel/fs/gen8+: Fix r127 dst/src overlap RA workaround for EOT
H A D20.3.0.rst477 - pan/mdg: Fix printing of r26 ld/st sources post-RA
4095 - aco: always use p_parallelcopy for pre-RA copies
4570 - aco: Fix integer overflows when emitting parallel copies during RA
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md89 The register allocator works on SSA (as opposed to LLVM's which works on virtual registers). The SSA properties guarantee that there are always as many registers available as needed. The problem is that some instructions require a vector of neighboring registers to be available, but the free regs might be scattered. In this case, the register allocator inserts shuffle code (moving some temporaries to other registers) to make space for the variable. The assumption is that it is (almost) always better to have a few more moves than to sacrifice a wave. The RA does SSA-reconstruction on the fly, which makes its runtime linear.
232 * `validatera` - Perform a RA (register allocation) validation.
/xsrc/external/mit/MesaLib/dist/docs/
H A Denvvars.rst735 validate register assignment of ACO IR and catches many RA bugs
/xsrc/external/mit/MesaLib.old/dist/src/compiler/spirv/
H A Dspirv.core.grammar.json5313 "enumerant" : "RA",

Completed in 81 milliseconds

12