Searched refs:READ_REG32 (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dlx_vga.c40 int data = READ_REG32(DC3_GENERAL_CFG);
H A Dgx_regacc.c110 value = READ_REG32(offset);
H A Dgx_driver.c822 temp = READ_REG32(MDC_DV_CTL);
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Ddisp_gu2.c63 READ_REG32(MDC_UNLOCK);
79 READ_REG32(MDC_UNLOCK);
100 READ_REG32(MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK |
102 lock = READ_REG32(MDC_UNLOCK);
199 unlock = READ_REG32(MDC_UNLOCK);
203 gcfg = READ_REG32(MDC_GENERAL_CFG);
204 dcfg = READ_REG32(MDC_DISPLAY_CFG);
280 temp = READ_REG32(MDC_DV_CTL);
292 vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000;
526 unlock = READ_REG32(MDC_UNLOC
[all...]
H A Ddisp_gu1.c57 READ_REG32(DC_UNLOCK);
102 READ_REG32(DC_UNLOCK);
109 READ_REG32(DC_UNLOCK);
196 unlock = READ_REG32(DC_UNLOCK);
200 gcfg = READ_REG32(DC_GENERAL_CFG);
201 tcfg = READ_REG32(DC_TIMING_CFG);
235 lock = READ_REG32(DC_UNLOCK);
236 ocfg = READ_REG32(DC_OUTPUT_CFG) & ~(DC_OCFG_8BPP | DC_OCFG_555);
290 unlock = READ_REG32(DC_UNLOCK);
294 gcfg = READ_REG32(DC_GENERAL_CF
[all...]
H A Dgfx_defs.h48 #define READ_REG32(offset) \ macro
H A Dvid_5530.c858 if (READ_REG32(DC_GENERAL_CFG) & DC_GCFG_VCLK_DIV)
H A Dtv_fs450.c287 *p_data = READ_REG32(phys_addr);
/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Ddisp_gu2.c290 READ_REG32(MDC_UNLOCK);
307 READ_REG32(MDC_UNLOCK);
327 dcfg = READ_REG32(MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK |
329 lock = READ_REG32(MDC_UNLOCK);
433 unlock = READ_REG32(MDC_UNLOCK);
438 gcfg = READ_REG32(MDC_GENERAL_CFG);
439 dcfg = READ_REG32(MDC_DISPLAY_CFG);
520 temp = READ_REG32(MDC_DV_CTL);
533 vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000;
814 unlock = READ_REG32(MDC_UNLOC
[all...]
H A Ddisp_gu1.c273 READ_REG32(DC_UNLOCK);
316 READ_REG32(DC_UNLOCK);
322 READ_REG32(DC_UNLOCK);
415 unlock = READ_REG32(DC_UNLOCK);
420 gcfg = READ_REG32(DC_GENERAL_CFG);
421 tcfg = READ_REG32(DC_TIMING_CFG);
458 lock = READ_REG32(DC_UNLOCK);
459 ocfg = READ_REG32(DC_OUTPUT_CFG) & ~(DC_OCFG_8BPP | DC_OCFG_555);
521 unlock = READ_REG32(DC_UNLOCK);
526 gcfg = READ_REG32(DC_GENERAL_CF
[all...]
H A Dgfx_defs.h152 #define READ_REG32(offset) \ macro
H A Dtv_fs450.c427 *p_data = READ_REG32(phys_addr);
/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vg.c65 READ_REG32(DC3_UNLOCK);
636 unlock = READ_REG32(DC3_UNLOCK);
653 temp = READ_REG32(DC3_GENERAL_CFG) & ~DC3_GCFG_VGAE;
672 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
686 temp = READ_REG32(DC3_COLOR_KEY);
706 gcfg = READ_REG32(DC3_GENERAL_CFG);
712 dcfg = READ_REG32(DC3_DISPLAY_CFG);
766 genlk_ctl = READ_REG32(DC3_GENLK_CTL) & ~(DC3_GC_ALPHA_FLICK_ENABLE |
862 temp = READ_REG32(DC3_DV_CTL);
929 temp = ((READ_REG32(DC3_V_ACTIVE_TIMIN
[all...]
H A Dcim_df.c131 lock = READ_REG32(DC3_UNLOCK);
132 vg_line = READ_REG32(DC3_LINE_SIZE);
133 gcfg = READ_REG32(DC3_GENERAL_CFG);
264 if (READ_REG32(DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) {
291 unsigned long lock = READ_REG32(DC3_UNLOCK);
337 gfxscale = READ_REG32(DC3_GFX_SCALE);
338 fbactive = READ_REG32(DC3_FB_ACTIVE);
408 unlock = READ_REG32(DC3_UNLOCK);
409 gcfg = READ_REG32(DC3_GENERAL_CFG) & ~DC3_GCFG_VDSE;
413 downscale = READ_REG32(DC3_VID_DS_DELT
[all...]
H A Dcim_vop.c48 unlock = READ_REG32(DC3_UNLOCK);
65 htotal = ((READ_REG32(DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1;
66 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
117 temp = READ_REG32(DC3_VBI_EVEN_CTL) & ~DC3_VBI_EVEN_CTL_OFFSET_MASK;
126 temp = READ_REG32(DC3_VBI_ODD_CTL) & ~DC3_VBI_ODD_CTL_OFFSET_MASK;
152 unlock = READ_REG32(DC3_UNLOCK);
153 temp = READ_REG32(DC3_VBI_EVEN_CTL);
187 unlock = READ_REG32(DC3_UNLOCK);
188 delta = READ_REG32(DC3_VID_DS_DELTA) & DC3_DS_DELTA_MASK;
398 READ_REG32(DC3_VID_DS_DELT
[all...]
H A Dcim_vip.c674 unlock = READ_REG32(DC3_UNLOCK);
675 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
728 unlock = READ_REG32(DC3_UNLOCK);
729 temp = READ_REG32(DC3_GENLK_CTL);
1109 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_GENLK_ACTIVE)
1124 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_VIP_VID_OK)
1387 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
1422 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_GENLOCK_ENABLE)
H A Dcim_defs.h43 #define READ_REG32(offset) \ macro
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_regacc.c198 value = READ_REG32(offset);
H A Dnsc_gx2_driver.c1150 temp = READ_REG32(MDC_DV_CTL);

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