| /xsrc/external/mit/MesaLib/dist/src/freedreno/perfcntrs/ |
| H A D | freedreno_perfcntr.h | 103 .select_reg = REG(_sel), .counter_reg_lo = REG(_lo), \
104 .counter_reg_hi = REG(_hi), \
108 .select_reg = REG(_sel), .counter_reg_lo = REG(_lo), \
109 .counter_reg_hi = REG(_hi), .enable = REG(_en), .clear = REG(_clr), \
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| H A D | fd5_perfcntr.c | 35 #define REG(_x) REG_A5XX_ ## _x macro
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| H A D | fd6_perfcntr.c | 36 #define REG(_x) REG_A6XX_ ## _x macro
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| H A D | fd2_perfcntr.c | 34 #define REG(_x) REG_A2XX_ ## _x macro
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/decode/ |
| H A D | cffdec.c | 351 r = regbase("CP_SCRATCH[0].REG");
540 #define REG(x, fxn) { #x, fxn } macro
549 REG(CP_SCRATCH_REG0, reg_dump_scratch),
550 REG(CP_SCRATCH_REG1, reg_dump_scratch),
551 REG(CP_SCRATCH_REG2, reg_dump_scratch),
552 REG(CP_SCRATCH_REG3, reg_dump_scratch),
553 REG(CP_SCRATCH_REG4, reg_dump_scratch),
554 REG(CP_SCRATCH_REG5, reg_dump_scratch),
555 REG(CP_SCRATCH_REG6, reg_dump_scratch),
556 REG(CP_SCRATCH_REG
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/tools/ |
| H A D | i965_lex.l | 26 %x REG
50 null { BEGIN(REG); return NULL_TOKEN; }
197 <REG>"<" { return LANGLE; }
198 <REG>[0-9][0-9]* {
202 <REG>">" { return RANGLE; }
203 <REG>"," { return COMMA; }
204 <REG>"." { BEGIN(DOTSEL); return DOT; }
205 <REG>";" { return SEMICOLON; }
213 BEGIN(REG);
217 <REG>
[all...] |
| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/os-support/ |
| H A D | int10Defines.h | 40 (((type *)&(((struct vm86_struct *)REG->cpuRegs)->regs.name))[num])
|
| /xsrc/external/mit/xorg-server/dist/hw/xfree86/os-support/ |
| H A D | int10Defines.h | 40 (((type *)&(((struct vm86_struct *)REG->cpuRegs)->regs.name))[num])
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/ |
| H A D | fd5_perfcntr.c | 33 #define REG(_x) REG_A5XX_ ## _x macro
36 .select_reg = REG(_sel), \
37 .counter_reg_lo = REG(_lo), \
38 .counter_reg_hi = REG(_hi), \
42 .select_reg = REG(_sel), \
43 .counter_reg_lo = REG(_lo), \
44 .counter_reg_hi = REG(_hi), \
45 .enable = REG(_en), \
46 .clear = REG(_clr), \
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/ |
| H A D | fd6_perfcntr.c | 33 #define REG(_x) REG_A6XX_ ## _x macro
36 .select_reg = REG(_sel), \
37 .counter_reg_lo = REG(_lo), \
38 .counter_reg_hi = REG(_hi), \
42 .select_reg = REG(_sel), \
43 .counter_reg_lo = REG(_lo), \
44 .counter_reg_hi = REG(_hi), \
45 .enable = REG(_en), \
46 .clear = REG(_clr), \
|
| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/i2c/ |
| H A D | bt829.c | 705 #define DUMPREG(REG) \
707 #REG,REG,BTREAD(REG))
|
| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/int10/ |
| H A D | helper_mem.c | 23 #define REG pInt macro
|
| H A D | helper_exec.c | 50 #define REG pInt macro
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| H A D | xf86int10.c | 18 #define REG pInt macro
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| /xsrc/external/mit/xorg-server.old/dist/hw/xfree86/os-support/linux/int10/vm86/ |
| H A D | linux_vm86.c | 15 #define REG pInt macro
|
| /xsrc/external/mit/xorg-server/dist/hw/xfree86/int10/ |
| H A D | helper_mem.c | 23 #define REG pInt macro
|
| H A D | helper_exec.c | 51 #define REG pInt macro
|
| H A D | xf86int10.c | 18 #define REG pInt macro
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| /xsrc/external/mit/xorg-server/dist/hw/xfree86/os-support/linux/int10/vm86/ |
| H A D | linux_vm86.c | 15 #define REG pInt macro
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/.gitlab-ci/reference/ |
| H A D | afuc_test.asm | 30 mov $02, 0x0883 ; CP_SCRATCH[0].REG
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a2xx/ |
| H A D | fd2_perfcntr.c | 32 #define REG(_x) REG_A2XX_ ## _x macro
35 .select_reg = REG(_sel), \
36 .counter_reg_lo = REG(_lo), \
37 .counter_reg_hi = REG(_hi), \
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 21.1.0.rst | 1852 - nir-to-tgsi: Fix handling of partial writemasks on SSA/REG decls.
|