Searched refs:REG_TYPE_S (Results 1 - 25 of 29) sorted by relevance

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/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h70 #define FS_S0 ((REG_TYPE_S << 8) | 0)
71 #define FS_S1 ((REG_TYPE_S << 8) | 1)
72 #define FS_S2 ((REG_TYPE_S << 8) | 2)
73 #define FS_S3 ((REG_TYPE_S << 8) | 3)
225 if (REG_TYPE(reg) != REG_TYPE_S)
253 if (REG_TYPE(sampler_reg) != REG_TYPE_S)
H A Di915_reg.h527 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h56 #define REG_TYPE_S 3 /* sampler */ macro
274 #define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
275 #define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
276 #define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
277 #define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
362 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
H A Di915_reg.h506 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h56 #define REG_TYPE_S 3 /* sampler */ macro
274 #define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
275 #define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
276 #define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
277 #define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
362 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
H A Di915_reg.h506 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_debug_fp.c251 if (type == REG_TYPE_S)
255 if (type == REG_TYPE_S) {
H A Di915_fpc_emit.c86 } else if (type == REG_TYPE_S) {
H A Di915_reg.h491 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h509 #define REG_TYPE_S 3 /* sampler */ macro
903 #define REG_TYPE_S 3 /* sampler */ macro
1121 #define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
1122 #define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
1123 #define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
1124 #define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
1209 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h509 #define REG_TYPE_S 3 /* sampler */ macro
903 #define REG_TYPE_S 3 /* sampler */ macro
1121 #define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
1122 #define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
1123 #define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
1124 #define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
1209 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_program.h24 #define REG_TYPE_S 3 /* sampler */ macro
H A Di915_xvmc.c193 i915_inst_decl(&pixel_shader_program->inst1[i], REG_TYPE_S, 0,
199 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
225 i915_inst_decl(&pixel_shader_program->inst2[i], REG_TYPE_S, 1,
231 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
266 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 0,
270 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 1,
276 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
283 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
H A Di915_reg.h506 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_program.h24 #define REG_TYPE_S 3 /* sampler */ macro
H A Di915_xvmc.c193 i915_inst_decl(&pixel_shader_program->inst1[i], REG_TYPE_S, 0,
199 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
225 i915_inst_decl(&pixel_shader_program->inst2[i], REG_TYPE_S, 1,
231 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
266 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 0,
270 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 1,
276 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
283 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
H A Di915_reg.h506 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_program.h24 #define REG_TYPE_S 3 /* sampler */ macro
H A Di915_xvmc.c237 i915_inst_decl(&pixel_shader_program->inst1[i], REG_TYPE_S, 0, D0_SAMPLE_TYPE_2D);
242 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
265 i915_inst_decl(&pixel_shader_program->inst2[i], REG_TYPE_S, 1, D0_SAMPLE_TYPE_2D);
270 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
299 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 0, D0_SAMPLE_TYPE_2D);
302 i915_inst_decl(&pixel_shader_program->inst3[i], REG_TYPE_S, 1, D0_SAMPLE_TYPE_2D);
307 src1 = UREG(REG_TYPE_S, 0); /* SAMPLER */
313 src1 = UREG(REG_TYPE_S, 1); /* SAMPLER */
1354 i915_inst_decl(inst, REG_TYPE_S, 0, D0_SAMPLE_TYPE_2D);
1357 i915_inst_decl(inst, REG_TYPE_S,
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_fpc_emit.c90 else if (type == REG_TYPE_S) {
H A Di915_reg.h518 #define REG_TYPE_S 3 /* sampler */ macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_reg.h390 #define REG_TYPE_S 3 /* sampler */ macro
H A Di915_program.c121 else if (type == REG_TYPE_S) {
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_reg.h390 #define REG_TYPE_S 3 /* sampler */ macro
H A Di915_program.c121 else if (type == REG_TYPE_S) {

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