Searched refs:R_028028_DB_STENCIL_CLEAR (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/MesaLib.old/src/gallium/drivers/r600/
H A Degd_tables.h950 {15370, R_028028_DB_STENCIL_CLEAR},
/xsrc/external/mit/MesaLib/src/gallium/drivers/r600/
H A Degd_tables.h950 {15370, R_028028_DB_STENCIL_CLEAR},
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c1237 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1378 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cmd_buffer.c1989 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1996 radeon_set_context_reg(cs, R_028028_DB_STENCIL_CLEAR, ds_clear_value.stencil);
2158 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Devergreen_state.c2813 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3223 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
H A Devergreend.h1958 #define R_028028_DB_STENCIL_CLEAR 0x00028028 macro
H A Dr600_state.c2370 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
H A Dr600d.h2382 #define R_028028_DB_STENCIL_CLEAR 0x028028 macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Devergreen_state.c2819 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
3229 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
H A Devergreend.h1958 #define R_028028_DB_STENCIL_CLEAR 0x00028028 macro
H A Dr600_state.c2373 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
H A Dr600d.h2382 #define R_028028_DB_STENCIL_CLEAR 0x028028 macro
/xsrc/external/mit/MesaLib.old/src/amd/common/
H A Dsid_tables.h828 {15497, R_028028_DB_STENCIL_CLEAR, 1, 1234},
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3255 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3256 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c3376 radeon_set_context_reg_seq(R_028028_DB_STENCIL_CLEAR, 2);
3377 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dgfx9d.h3955 #define R_028028_DB_STENCIL_CLEAR 0x028028 macro
H A Dsid.h5109 #define R_028028_DB_STENCIL_CLEAR 0x028028 macro
/xsrc/external/mit/MesaLib/src/amd/common/
H A Damdgfxregs.h8307 #define R_028028_DB_STENCIL_CLEAR 0x028028 macro
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