| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_ir.h | 307 struct RegClass { struct in namespace:aco
337 RegClass() = default;
338 constexpr RegClass(RC rc_) : rc(rc_) {} function in struct:aco::RegClass
339 constexpr RegClass(RegType type, unsigned size) function in struct:aco::RegClass
353 constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); }
354 constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); }
356 static constexpr RegClass get(RegType type, unsigned bytes)
359 return RegClass(typ
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| H A D | aco_reindex_ssa.cpp | 33 std::vector<RegClass> temp_rc = {s1};
44 RegClass rc = def.regClass();
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| H A D | aco_instruction_selection.h | 45 std::fill_n(temps, VARYING_SLOT_MAX * 4u, Temp(0, RegClass::v1));
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| H A D | aco_instruction_selection_setup.cpp | 240 RegClass
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components);
246 return RegClass::get(type, components * bitsize / 8u);
451 RegClass* regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id;
559 RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components,
567 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
741 RegClass rc = get_reg_class(ctx, type, intrinsic->dest.ssa.num_components,
754 RegClass rc =
768 RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size);
788 RegClass r
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| H A D | aco_reduce_assign.cpp | 60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear());
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear());
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| H A D | aco_register_allocation.cpp | 41 unsigned idx, RegClass rc);
43 RegClass rc);
45 get_subdword_definition_info(Program* program, const aco_ptr<Instruction>& instr, RegClass rc);
50 RegClass rc;
54 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {}
167 get_stride(RegClass rc)
197 RegClass rc;
199 DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc_, int operand) : rc(rc_)
213 rc = RegClass::get(rc.type(), info.second);
264 void block(PhysReg start, RegClass r
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| H A D | aco_lower_to_hw_instr.cpp | 304 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1;
391 RegClass rc = RegClass(RegType::vgpr, size);
431 RegClass rc = RegClass(RegType::vgpr, size);
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size));
1003 RegClass op_cls = src.op.regClass().resize(bytes);
1204 Definition(lo_reg, RegClass::get(RegType::vgpr, def.physReg().byte()));
1206 Definition(lo_reg, RegClass::get(RegType::vgpr, lo_half.bytes() + op.bytes()));
1521 RegClass r
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| H A D | aco_instruction_selection.cpp | 151 RegClass rc = RegClass(mask.regClass().type(), 1);
338 emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
379 RegClass rc;
387 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword();
389 rc = RegClass(vec_src.type(), vec_src.size() / num_components);
432 emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
536 RegClass rc = RegClass(RegType::vgpr, component_size).as_subdword();
555 vec = bld.pseudo(aco_opcode::p_as_uniform, bld.def(RegClass(RegTyp
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| H A D | aco_optimizer_postRA.cpp | 109 last_writer_idx(pr_opt_ctx& ctx, PhysReg physReg, RegClass rc)
143 is_clobbered_since(pr_opt_ctx& ctx, PhysReg reg, RegClass rc, const Idx& idx)
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| H A D | aco_live_var_analysis.cpp | 215 RegClass rc = program->temp_rc[t];
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| H A D | aco_lower_phis.cpp | 326 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size()));
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| H A D | aco_spill.cpp | 78 std::vector<std::pair<RegClass, std::unordered_set<uint32_t>>> interferences;
133 uint32_t allocate_spill_id(RegClass rc)
1440 RegClass other_rc = ctx.interferences[other].first;
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| H A D | aco_insert_waitcnt.cpp | 570 insert_wait_entry(wait_ctx& ctx, PhysReg reg, RegClass rc, wait_event event, bool wait_on_read,
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| H A D | aco_print_ir.cpp | 90 print_reg_class(const RegClass rc, FILE* output)
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| H A D | helpers.cpp | 119 RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0');
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| H A D | test_to_hw_instr.cpp | 712 RegClass v1_linear = v1.as_linear();
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 1253 - aco: refactor get_reg() to take Temp instead of RegClass
3581 - aco: add and use RegClass::get() helper
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| H A D | 21.3.0.rst | 3587 - aco: add RegClass::is_linear_vgpr helper
3588 - aco: add and use RegClass::resize helper
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| H A D | 21.2.0.rst | 1559 - aco: simplify Phi RegClass selection
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