Searched refs:RegType (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_instruction_selection_setup.cpp241 get_reg_class(isel_context* ctx, RegType type, unsigned components, unsigned bitsize)
244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components);
464 RegType type =
465 nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
523 case nir_op_sdot_2x16_iadd_sat: type = RegType::vgpr; break;
549 type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type;
553 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr)
554 type = RegType::vgpr;
567 RegClass rc = get_reg_class(ctx, RegType
[all...]
H A Daco_validate.cpp313 check(instr->definitions[0].getTemp().type() == RegType::sgpr,
316 check(instr->definitions[0].getTemp().type() == RegType::vgpr,
327 check(i != 1 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
330 check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
337 check(i != 0 || (op.isTemp() && op.regClass().type() == RegType::vgpr),
339 check(i == 0 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
347 check(i != 2 || (op.isTemp() && op.regClass().type() == RegType::vgpr &&
350 check(i == 2 || (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
355 if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
374 check(instr->definitions[0].getTemp().type() == RegType
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H A Daco_spill.cpp200 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear())
410 if (op.regClass().type() == RegType::vgpr && op.regClass().is_linear())
524 RegType type = RegType::vgpr;
527 if (type == RegType::vgpr && loop_demand.vgpr <= ctx.target_pressure.vgpr)
528 type = RegType::sgpr;
530 if (type == RegType::sgpr && loop_demand.sgpr <= ctx.target_pressure.sgpr)
539 (ctx.remat.count(pair.first) && type == RegType::sgpr)) &&
548 if (type == RegType::sgpr)
550 type = RegType
[all...]
H A Daco_lower_to_cssa.cpp103 if (def.regClass().type() == RegType::sgpr && !op.isTemp()) {
173 idom = b.regClass().type() == RegType::vgpr ? ctx.program->blocks[idom].logical_idom
197 std::vector<uint32_t>& preds = var.type() == RegType::vgpr
351 pred = copy.op.regClass().type() == RegType::vgpr ? ctx.program->blocks[pred].logical_idom
387 emit_copies_block(Builder& bld, std::map<uint32_t, ltg_node>& ltg, RegType type)
466 bool is_vgpr = cp.def.regClass().type() == RegType::vgpr;
492 emit_copies_block(bld, ltg, RegType::vgpr);
500 emit_copies_block(bld, ltg, RegType::sgpr);
H A Daco_reduce_assign.cpp60 Temp reduceTmp(0, RegClass(RegType::vgpr, maxSize).as_linear());
61 Temp vtmp(0, RegClass(RegType::vgpr, maxSize).as_linear());
H A Daco_instruction_selection.cpp270 if (val.type() == RegType::sgpr) {
272 return bld.copy(bld.def(RegType::vgpr, val.size()), val);
274 assert(val.type() == RegType::vgpr);
354 assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
381 if (vec_src.type() == RegType::sgpr) {
387 rc = RegClass(RegType::vgpr, vec_src.bytes() / num_components).as_subdword();
415 if (dst.type() == RegType::sgpr)
433 if (dst.type() == RegType::sgpr)
536 RegClass rc = RegClass(RegType
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H A Daco_lower_to_hw_instr.cpp391 RegClass rc = RegClass(RegType::vgpr, size);
431 RegClass rc = RegClass(RegType::vgpr, size);
433 Operand src0(src0_reg, RegClass(src0_reg.reg() >= 256 ? RegType::vgpr : RegType::sgpr, size));
814 if (reduction_needs_last_op && dst.regClass().type() == RegType::vgpr) {
827 if (dst.regClass().type() == RegType::sgpr) {
866 assert(input_data.regClass().type() == RegType::vgpr);
935 assert(input.regClass().type() == RegType::vgpr);
979 if (ctx->program->chip_class < GFX10 && src.def.regClass().type() == RegType::vgpr)
981 unsigned max_align = src.def.regClass().type() == RegType
[all...]
H A Daco_ir.cpp212 if (chip < GFX9 && !instr->operands[i].isOfType(RegType::vgpr))
223 if (chip < GFX9 && !instr->operands[0].isOfType(RegType::vgpr))
284 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
321 if (instr->operands.size() > 1 && !instr->operands[1].isOfType(RegType::vgpr))
551 if (def.getTemp().type() == RegType::vgpr)
680 (instr->operands[0].isTemp() && instr->operands[0].getTemp().type() == RegType::sgpr))
H A Daco_optimizer.cpp510 [](const Definition& def) { return def.regClass().type() == RegType::vgpr; });
513 if (temp.type() == RegType::vgpr && !vgpr)
530 if (temp.type() == RegType::sgpr && !can_accept_sgpr)
534 if (temp.type() == RegType::sgpr && !can_accept_sgpr)
604 return op.isTemp() && op.getTemp().type() == RegType::vgpr;
672 if (op.hasRegClass() && op.regClass().type() == RegType::sgpr) {
834 (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) {
878 (tmp.type() == RegType::vgpr || ctx.program->chip_class >= GFX9)) {
899 if (info.is_extract() && (info.instr->operands[0].getTemp().type() == RegType::vgpr ||
900 op.getTemp().type() == RegType
[all...]
H A Daco_ir.h300 enum class RegType { enum in namespace:aco
339 constexpr RegClass(RegType type, unsigned size)
340 : rc((RC)((type == RegType::vgpr ? 1 << 5 : 0) | size))
346 constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; }
356 static constexpr RegClass get(RegType type, unsigned bytes)
358 if (type == RegType::sgpr) {
369 return get(RegType::vgpr, bytes).as_linear();
415 constexpr RegType typ
[all...]
H A Daco_insert_NOPs.cpp412 if (def.regClass().type() != RegType::sgpr) {
443 if (!op.isConstant() && !op.isUndefined() && op.regClass().type() == RegType::sgpr)
504 if (def.regClass().type() == RegType::sgpr) {
542 instr->operands[1].regClass().type() == RegType::vgpr &&
612 { return def.getTemp().type() == RegType::sgpr; });
H A Daco_register_allocation.cpp169 if (rc.type() == RegType::vgpr) {
184 get_reg_bounds(Program* program, RegType type)
186 if (type == RegType::vgpr) {
397 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr);
703 if (rc.type() == RegType::vgpr) {
850 (rc.type() == RegType::vgpr) ? (256 + ctx.max_used_vgpr) : ctx.max_used_sgpr;
1318 if (rc.type() == RegType::sgpr && reg % get_stride(rc) != 0)
1325 bool is_vcc = rc.type() == RegType::sgpr && vcc_win.contains(reg_win);
1345 increase_register_file(ra_ctx& ctx, RegType typ
[all...]
H A Daco_live_var_analysis.cpp203 assert(definition.getTemp().type() == RegType::sgpr);
249 if (insn->opcode == aco_opcode::p_phi && operand.getTemp().type() == RegType::sgpr) {
252 assert(operand.getTemp().type() == RegType::sgpr);
H A Daco_lower_phis.cpp325 assert(phi_src.regClass().type() == RegType::sgpr);
326 Temp tmp = bld.tmp(RegClass(RegType::vgpr, phi_src.size()));
H A Daco_optimizer_postRA.cpp91 assert(def.regClass().type() != RegType::sgpr || def.physReg().reg() <= 255);
92 assert(def.regClass().type() != RegType::vgpr || def.physReg().reg() >= 256);
H A Daco_print_ir.cpp94 } else if (rc.type() == RegType::sgpr) {
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dhelpers.cpp119 RegClass cls(input_spec[i * 3] == 'v' ? RegType::vgpr : RegType::sgpr, input_spec[i * 3 + 1] - '0');
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.2.0.rst1552 - aco: relax validation rules for p_reduce dst RegType

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