Searched refs:S5_WRITEDISABLE_ALPHA (Results 1 - 17 of 17) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/ |
| H A D | i915_state_emit.c | 138 { PIPE_FORMAT_R8G8B8A8_UNORM, { S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_RED, S5_WRITEDISABLE_ALPHA}},
139 { PIPE_FORMAT_R8G8B8X8_UNORM, { S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_RED, S5_WRITEDISABLE_ALPHA}},
140 { PIPE_FORMAT_L8_UNORM, { S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE, 0, 0, S5_WRITEDISABLE_ALPHA}},
141 { PIPE_FORMAT_I8_UNORM, { S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE, 0, 0, S5_WRITEDISABLE_ALPHA}},
142 { PIPE_FORMAT_A8_UNORM, { 0, 0, 0, S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA}},
143 { 0, { S5_WRITEDISABLE_RED, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_ALPHA}}
160 S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA );
169 if (imm & S5_WRITEDISABLE_ALPHA)
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| H A D | i915_reg.h | 393 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| H A D | i915_state.c | 161 cso_data->LIS5 |= S5_WRITEDISABLE_ALPHA;
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/ |
| H A D | intel_reg.h | 140 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| H A D | i915_state.c | 707 tmp |= S5_WRITEDISABLE_ALPHA;
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/ |
| H A D | intel_reg.h | 140 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| H A D | i915_state.c | 707 tmp |= S5_WRITEDISABLE_ALPHA;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/ |
| H A D | i915_state_emit.c | 133 S5_WRITEDISABLE_ALPHA,
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| H A D | i915_reg.h | 372 #define S5_WRITEDISABLE_ALPHA (1 << 31) macro
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| H A D | i915_state.c | 202 cso_data->LIS5 |= S5_WRITEDISABLE_ALPHA;
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| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| H A D | i915_reg.h | 397 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| H A D | i915_reg.h | 397 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| H A D | i915_reg.h | 397 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| H A D | i915_reg.h | 397 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| H A D | i915_reg.h | 413 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| H A D | gen3_render.h | 400 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| H A D | gen3_render.h | 400 #define S5_WRITEDISABLE_ALPHA (1<<31) macro
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