Searched refs:S5_WRITEDISABLE_GREEN (Results 1 - 17 of 17) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_state_emit.c138 { PIPE_FORMAT_R8G8B8A8_UNORM, { S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_RED, S5_WRITEDISABLE_ALPHA}},
139 { PIPE_FORMAT_R8G8B8X8_UNORM, { S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_RED, S5_WRITEDISABLE_ALPHA}},
140 { PIPE_FORMAT_L8_UNORM, { S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE, 0, 0, S5_WRITEDISABLE_ALPHA}},
141 { PIPE_FORMAT_I8_UNORM, { S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE, 0, 0, S5_WRITEDISABLE_ALPHA}},
142 { PIPE_FORMAT_A8_UNORM, { 0, 0, 0, S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN | S5_WRITEDISABLE_BLUE | S5_WRITEDISABLE_ALPHA}},
143 { 0, { S5_WRITEDISABLE_RED, S5_WRITEDISABLE_GREEN, S5_WRITEDISABLE_BLUE, S5_WRITEDISABLE_ALPHA}}
159 uint fixup_imm = imm & ~( S5_WRITEDISABLE_RED | S5_WRITEDISABLE_GREEN |
165 if (imm & S5_WRITEDISABLE_GREEN)
H A Di915_reg.h395 #define S5_WRITEDISABLE_GREEN (1<<29) macro
H A Di915_state.c155 cso_data->LIS5 |= S5_WRITEDISABLE_GREEN;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h142 #define S5_WRITEDISABLE_GREEN (1<<29) macro
H A Di915_state.c703 tmp |= S5_WRITEDISABLE_GREEN;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_reg.h142 #define S5_WRITEDISABLE_GREEN (1<<29) macro
H A Di915_state.c703 tmp |= S5_WRITEDISABLE_GREEN;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_emit.c131 S5_WRITEDISABLE_GREEN,
H A Di915_reg.h374 #define S5_WRITEDISABLE_GREEN (1 << 29) macro
H A Di915_state.c196 cso_data->LIS5 |= S5_WRITEDISABLE_GREEN;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_reg.h399 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h399 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_reg.h399 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h399 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_reg.h415 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h402 #define S5_WRITEDISABLE_GREEN (1<<29) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h402 #define S5_WRITEDISABLE_GREEN (1<<29) macro

Completed in 36 milliseconds