| /xsrc/external/mit/xf86-video-ast/dist/src/ |
| H A D | ast_mode.h | 92 UCHAR SEQ[4]; member in struct:__anon502f03860108
|
| H A D | ast.h | 122 UCHAR SEQ[4]; member in struct:_ASTRegRec
|
| H A D | ast_driver.c | 1386 GetIndexReg(SEQ_PORT, (UCHAR) (i), astReg->SEQ[i]);
1469 SetIndexReg(SEQ_PORT, (UCHAR) (i), astReg->SEQ[i]);
|
| H A D | ast_mode.c | 731 jReg = pStdModePtr->SEQ[i];
|
| /xsrc/external/mit/xf86-video-apm/dist/src/ |
| H A D | apm_driver.c | 1170 ApmReg->SEQ[0x1B] = ApmReadSeq(0x1B);
1171 ApmReg->SEQ[0x1C] = ApmReadSeq(0x1C);
1185 ApmWriteSeq(0x1C, ApmReg->SEQ[0x1C]);
1225 ApmReg->SEQ[0x1B] = rdinx(pApm->xport, 0x1B);
1226 ApmReg->SEQ[0x1C] = rdinx(pApm->xport, 0x1C);
1518 ApmReg->SEQ[0x1B] = 0x20;
1519 ApmReg->SEQ[0x1C] = 0x2F;
1522 ApmReg->SEQ[0x1B] = 0x24;
1524 ApmReg->SEQ[0x1C] = 0x2F;
1526 ApmReg->SEQ[
[all...] |
| H A D | apm.h | 74 unsigned char SEQ[NoSEQRegs]; member in struct:__anon29656e4e0208
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 76 OP12(SEQ)
|
| H A D | tgsi_info_opcodes.h | 46 OPCODE(1, 2, COMP, SEQ)
|
| /xsrc/external/mit/MesaLib/dist/src/amd/registers/ |
| H A D | pkt3.json | 388 {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"},
412 {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"}
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 81 OP12(SEQ)
|
| H A D | tgsi_info_opcodes.h | 46 OPCODE(1, 2, COMP, SEQ)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv30/ |
| H A D | nvfx_vertprog.c | 650 nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
|
| H A D | nvfx_fragprog.c | 693 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv30/ |
| H A D | nvfx_vertprog.c | 651 nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
|
| H A D | nvfx_fragprog.c | 693 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler.c | 1793 INSTR(SEQ, trans_instr, .opc = INST_OPCODE_SET, .src = {0, 1, -1}, .cond = INST_CONDITION_EQ),
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_tgsi.c | 1837 INSTR(SEQ, trans_instr, .opc = INST_OPCODE_SET, .src = {0, 1, -1}, .cond = INST_CONDITION_EQ),
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/ |
| H A D | tgsi.rst | 451 .. opcode:: SEQ - Set On Equal
1441 Same comparison as SEQ but returns integer instead of 1.0/0.0 float
|
| /xsrc/external/mit/MesaLib/dist/docs/gallium/ |
| H A D | tgsi.rst | 454 .. opcode:: SEQ - Set On Equal
1475 Same comparison as SEQ but returns integer instead of 1.0/0.0 float
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 823 NV50_IR_OPCODE_CASE(SEQ, SET);
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_from_tgsi.cpp | 764 NV50_IR_OPCODE_CASE(SEQ, SET);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/ |
| H A D | st_glsl_to_tgsi.cpp | 784 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
1461 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1462 * older GPUs implement SEQ using multiple instructions (i915 uses two
1638 /* Emit 1-3 AND operations to combine the SEQ results. */
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/ |
| H A D | st_glsl_to_tgsi.cpp | 863 casecomp(SEQ, FSEQ, USEQ, USEQ, DSEQ, U64SEQ, U64SEQ);
1540 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1541 * older GPUs implement SEQ using multiple instructions (i915 uses two
1706 /* Emit 1-3 AND operations to combine the SEQ results. */
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 21.2.0.rst | 2144 - i915g: Fix writemasking of SEQ/SNE/SSG.
|