Searched refs:SMEM (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME-ISA.md59 ## SMEM stores
62 the offset for SMEM stores must be in m0 if IMM == 0.
64 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
68 ## SMEM atomics
70 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
176 ## SMEM corrupts VCCZ on SI/CI
180 After issuing a SMEM instructions, we need to wait for the SMEM instructions to
202 ### SMEM store followed by a load with the same address
208 SMEM store
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H A Daco_opt_value_numbering.cpp97 case Format::SMEM: return hash_murmur_32<SMEM_instruction>(instr);
202 case Format::SMEM: {
338 case Format::SMEM:
H A Daco_insert_NOPs.cpp144 /* we break up SMEM clauses that contain stores or overwrite an
312 /* A SMEM clause is any group of consecutive SMEM instructions. The
318 * itself). In this case, we have to break the SMEM clause by inserting non
319 * SMEM instructions.
321 * SMEM clauses are only present on GFX8+, and only matter when XNACK is set.
327 /* break off from previous SMEM clause if needed */
448 if (!instr->isSALU() && instr->format != Format::SMEM)
474 if ((ctx.smem_clause || ctx.smem_write) && (NOPs || instr->format != Format::SMEM)) {
724 * Handle any VALU instruction writing an SGPR after an SMEM read
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H A Daco_opcodes.py59 SMEM = 6 variable in class:Format
86 elif self == Format.SMEM:
572 # SMEM instructions: sbase input (2 sgpr), potentially 2 offset inputs, 1 sdata input/output
573 # Unlike GFX10, GFX10.3 does not have SMEM store, atomic or scratch instructions
574 SMEM = { variable
663 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SMEM:
664 opcode(name, gfx7, gfx9, gfx10, Format.SMEM, InstrClass.SMem, is_atomic = "atomic" in name)
H A Daco_insert_waitcnt.cpp646 case Format::SMEM: {
H A Daco_ir.cpp172 case Format::SMEM: return instr->smem().sync;
H A Daco_print_ir.cpp337 case Format::SMEM: {
H A Daco_ir.h78 SMEM = 6, enumerator in enum:aco::Format
1097 constexpr bool isSMEM() const noexcept { return format == Format::SMEM; }
H A Daco_assembler.cpp180 case Format::SMEM: {
H A Daco_scheduler.cpp471 unsigned aliasing_storage; /* storage classes which are accessed (non-SMEM) */
472 unsigned aliasing_storage_smem; /* storage classes which are accessed (SMEM) */
667 /* break if we'd make the previous SMEM instruction stall */
682 if (candidate->format == Format::SMEM && current->operands[0].size() == 4 &&
814 /* break if we'd make the previous SMEM instruction stall */
H A Daco_validate.cpp525 case Format::SMEM: {
530 "SMEM operands must be sgpr", instr.get());
535 "SMEM offset must be constant or sgpr", instr.get());
538 "SMEM result must be sgpr", instr.get());
H A Daco_register_allocation.cpp1860 case Format::SMEM:
H A Daco_optimizer.cpp1177 /* SMEM: propagate constants and combine additions */
1203 smem.opcode, Format::SMEM, smem.operands.size() + 1, smem.definitions.size());
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.0.8.rst196 - aco: check instruction format before waiting for a previous SMEM
198 - aco: preserve more fields when combining additions into SMEM
H A D20.1.1.rst158 - aco: check instruction format before waiting for a previous SMEM
160 - aco: preserve more fields when combining additions into SMEM
H A D21.1.3.rst135 - aco: fix emitting literal offsets with SMEM on GFX7
H A D20.2.0.rst3812 - aco: check instruction format before waiting for a previous SMEM store
3813 - aco: preserve more fields when combining additions into SMEM
3861 - aco: only use SMEM if we can prove it's safe
3862 - aco: allow SMEM for some sub-dword accesses
3863 - radv/aco,aco: allow SMEM SSBO loads on GFX6/7
3902 - aco: allow overflow for some SMEM instructions
3905 - aco: use nir_addition_might_overflow to combine additions into SMEM
3939 - aco: disable SMEM stores on GFX10.3
H A D19.3.0.rst2853 - aco: keep can_reorder/barrier when combining addition into SMEM
3282 - aco: Support GFX10 SMEM in aco_assembler.
3301 - aco/gfx10: Wait for pending SMEM stores before loads
H A D20.0.0.rst735 - aco: fix SMEM offsets for SI/CI
3177 - aco: fix emitting SMEM instructions with no operands on GFX6-GFX7
3216 - aco: copy the literal offset of SMEM instructions to a temporary
H A D20.1.0.rst3580 - aco: be more careful about using SMEM for load_global
3584 - aco: use emit_load helper for VMEM/SMEM loads
3943 - aco: only break SMEM clauses if XNACK is enabled (mostly APUs)
H A D21.0.0.rst816 - aco: allow to schedule SALU/SMEM through exec changes
2688 - aco: don't use SMEM for SSBO stores
H A D21.3.0.rst1971 - iris: SMEM buffers on discrete platforms are coherent
3821 - radv: remove useless DISABLE_{ZMASK,SMEM}_EXPCLEAR_OPTIMIZATION state
H A D19.0.0.rst2004 - amd/common/vi+: enable SMEM loads with GLC=1
H A D20.3.0.rst114 - \[RADV/ACO\] ACO build error about SMEM operands
4286 - aco: validate that SMEM operands can use fixed registers
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json8815 "description": "anv: Disable the SMEM fallback for local memory",
20650 "description": "aco: remove SMEM constant/addition combining out of the loop",
20659 "description": "aco: skip &-4 before SMEM",
20668 "description": "aco: disallow SMEM offsets that are not multiples of 4",
22018 "description": "iris: Disable the SMEM fallback for CCS on XeHP",
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