Searched refs:TCS (Results 1 - 25 of 34) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_perfcounter.h84 TCS = 0x19, enumerator in enum:ac_pc_gpu_block
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.3.5.rst96 - glsl/linker: Fix unmatched TCS outputs being reduced to local
134 - glsl: fix recording of variables for XFB in TCS shaders
148 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
152 - glsl: TCS outputs can not be transform feedback candidates on GLES
H A D17.3.8.rst62 - anv/pipeline: fail if TCS/TES compile fail
H A D11.0.3.rst115 - radeonsi: handle fixed-func TCS shader create failure
116 - radeonsi: skip drawing if VS, TCS, TES, GS fail to compile or upload
H A D19.0.4.rst185 - radv: do not need to force emit the TCS regs on Vega20
190 - radv: only need to force emit the TCS regs on Vega10 and Raven1
H A D13.0.3.rst116 - radeonsi: wait for outstanding memory instructions in TCS barriers
H A D18.1.3.rst127 - radv: fix emitting the TCS regs on GFX9
H A D19.0.1.rst88 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
H A D21.1.4.rst153 - ac/nir: Update TCS output barriers with nir_var_mem_shared.
H A D13.0.4.rst170 - i965: Fix texturing in the vec4 TCS and GS backends.
H A D17.0.1.rst137 - mesa: Do (TCS && !TES) draw time validation in ES as well.
H A D17.2.6.rst135 - i965: Make L3 configuration atom listen for TCS/TES program updates.
H A D18.0.1.rst83 - anv/pipeline: fail if TCS/TES compile fail
H A D20.0.3.rst179 - nir: fix packing of TCS varyings not read by the TES
H A D12.0.2.rst272 - i965: Fix execution size of scalar TCS barrier setup code.
273 - i965: Fix barrier count shift in scalar TCS backend.
H A D13.0.6.rst190 - mesa: Do (TCS && !TES) draw time validation in ES as well.
H A D11.0.0.rst239 gl_TessLevel\* writes have no effect for all but the last TCS
H A D21.0.0.rst1918 - intel/compiler: Fix passthrough TCS regressions from program rename
2081 - nir: fix gathering TCS cross invocation access with lowered IO
2086 - radeonsi: don't allocate LDS for TCS outputs if they are not read
2089 - radeonsi: merge TCS and TCS epilog conditional blocks
2091 - radeonsi: if VS and TCS have the same number of threads, merge the conditonals
2093 - ac/llvm: prepare for passing VS->TCS IO via VGPRs
2094 - radeonsi: pass VS->TCS IO via VGPRs if VS and TCS have the same thread count
2095 - radeonsi: don't insert barrier between VS/TCS i
[all...]
H A D20.1.0.rst2051 - r600/sfn: Add VS for TCS shader skeleton
4126 - nir: fix packing of TCS varyings not read by the TES
4164 - aco: Implement load_view_index for TCS and TES.
4191 - aco: Only write TCS outputs to LDS when they are read by the TCS.
4192 - aco: Don't store TCS outputs to LDS when we're sure that none are
4202 - aco: Allow combining TCS output VMEM stores.
4204 - aco: Skip 2nd read of merged wave info when TCS in/out vertices are
4216 - aco: Don't store LS VS outputs to LDS when TCS doesn't need them.
4233 - aco: Only store TCS output
[all...]
H A D19.1.0.rst885 - iris: Add support for TCS passthrough
2031 - glsl: fix recording of variables for XFB in TCS shaders
2159 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
2361 - glsl: TCS outputs can not be transform feedback candidates on GLES
2857 - iris: compile a TCS...don't bother with passthrough yet
2974 - iris: use 0 for TCS passthrough program string ID
3102 - iris: Fix TCS/TES slot unification
3148 - iris: Fix failed to compile TCS message
4386 - radv: do not need to force emit the TCS regs on Vega20
4392 - radv: only need to force emit the TCS reg
[all...]
H A D19.0.0.rst468 - glsl/linker: Fix unmatched TCS outputs being reduced to local
1206 - glsl: fix recording of variables for XFB in TCS shaders
1502 - glsl: TCS outputs can not be transform feedback candidates on GLES
1614 TCS.
1992 - radeonsi: show the fixed function TCS in debug dumps
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md126 * TCS = Tessellation Control Shader, equivalent to D3D HS = Hull Shader
179 | with tess: | VS | TCS | | | TES | FS | `vertex_ls`, `tess_control_hs`, `tess_eval_vs`, `fragment_fs` |
181 | with both: | VS | TCS | TES | GS | GS copy| FS | `vertex_ls`, `tess_control_hs`, `tess_eval_es`, `geometry_gs`, `gs_copy_vs`, `fragment_fs` |
192 | with tess: | VS + TCS | | TES | FS | `vertex_tess_control_hs`, `tess_eval_vs`, `fragment_fs` |
194 | with both: | VS + TCS | TES + GS | GS copy| FS | `vertex_tess_control_hs`, `tess_eval_geometry_gs`, `gs_copy_vs`, `fragment_fs` |
204 | with tess: | VS + TCS | TES | FS | `vertex_tess_control_hs`, `tess_eval_ngg`, `fragment_fs` |
206 | with both: | VS + TCS | TES + GS | FS | `vertex_tess_control_hs`, `tess_eval_geometry_ngg`, `fragment_fs` |
H A Daco_instruction_selection_setup.cpp828 case MESA_SHADER_TESS_CTRL: sw_stage = sw_stage | SWStage::TCS; break;
861 else if (sw_stage == SWStage::TCS)
862 hw_stage = HWStage::HS; /* GFX6-8: TCS is a Hull Shader */
864 hw_stage = HWStage::HS; /* GFX9-10: VS+TCS merged into a Hull Shader */
H A Daco_ir.h138 storage_shared = 0x8, /* or TCS output */
139 storage_vmem_output = 0x10, /* GS or TCS output stores using VMEM */
1911 TCS = 1 << 2, /* Tessellation Control aka Hull Shader */ enumerator in enum:aco::SWStage
1919 VS_TCS = VS | TCS,
1941 LS, /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */
1942 HS, /* Hull shader: TCS on GFX6-8. Merged VS and TCS on GFX9-10. */
1993 static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_pipe.c50 { "tcs", DBG(TCS), "Print tessellation control shaders" },

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