Searched refs:UVD_BASE_INST0_SEG1 (Results 1 - 3 of 3) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_dec.h171 #define UVD_BASE_INST0_SEG1 0x00007E00 macro
176 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)
/xsrc/external/mit/libdrm/dist/tests/amdgpu/
H A Djpeg_tests.c95 #define UVD_BASE_INST0_SEG1 0x00007E00 macro
96 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_dec.h201 #define UVD_BASE_INST0_SEG1 0x00007E00 macro
206 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)

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