Searched refs:V3D_QPU_A_TMUWT (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_instr.c137 [V3D_QPU_A_TMUWT] = "tmuwt",
409 [V3D_QPU_A_TMUWT] = D,
567 inst->alu.add.op == V3D_QPU_A_TMUWT));
H A Dqpu_instr.h190 V3D_QPU_A_TMUWT, enumerator in enum:v3d_qpu_add_op
H A Dqpu_pack.c527 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_instr.c131 [V3D_QPU_A_TMUWT] = "tmuwt",
401 [V3D_QPU_A_TMUWT] = D,
550 inst->alu.add.op == V3D_QPU_A_TMUWT));
H A Dqpu_instr.h190 V3D_QPU_A_TMUWT, enumerator in enum:v3d_qpu_add_op
H A Dqpu_pack.c519 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dqpu_validate.c280 inst->alu.add.op == V3D_QPU_A_TMUWT)
H A Dvir_register_allocate.c50 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
63 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
H A Dqpu_schedule.c695 if (inst->alu.add.op == V3D_QPU_A_TMUWT)
1496 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
H A Dvir.c65 case V3D_QPU_A_TMUWT:
151 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dqpu_validate.c266 inst->alu.add.op == V3D_QPU_A_TMUWT)
H A Dvir.c62 case V3D_QPU_A_TMUWT:
135 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT) {
H A Dvir_register_allocate.c145 inst->qpu.alu.add.op == V3D_QPU_A_TMUWT)
H A Dqpu_schedule.c587 if (inst->alu.add.op == V3D_QPU_A_TMUWT)
1043 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)

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