Searched refs:V3D_QPU_WADDR_R0 (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dvir_to_qpu.c51 return qpu_magic(V3D_QPU_WADDR_R0 + acc);
109 assert(src.index >= V3D_QPU_WADDR_R0 &&
111 *mux = src.index - V3D_QPU_WADDR_R0 + V3D_QPU_MUX_R0;
153 if (waddr < V3D_QPU_WADDR_R0 || waddr > V3D_QPU_WADDR_R4)
157 V3D_QPU_MUX_R0 + (waddr - V3D_QPU_WADDR_R0)) {
H A Dvir_register_allocate.c674 temp_registers[i].index = (V3D_QPU_WADDR_R0 +
H A Dqpu_schedule.c190 case V3D_QPU_WADDR_R0:
194 &state->last_r[waddr - V3D_QPU_WADDR_R0],
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dvir_to_qpu.c103 assert(src.index >= V3D_QPU_WADDR_R0 &&
105 *mux = src.index - V3D_QPU_WADDR_R0 + V3D_QPU_MUX_R0;
147 if (waddr < V3D_QPU_WADDR_R0 || waddr > V3D_QPU_WADDR_R4)
151 V3D_QPU_MUX_R0 + (waddr - V3D_QPU_WADDR_R0)) {
H A Dvir_register_allocate.c857 temp_registers[i].index = (V3D_QPU_WADDR_R0 +
H A Dqpu_schedule.c221 case V3D_QPU_WADDR_R0:
225 &state->last_r[waddr - V3D_QPU_WADDR_R0],
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_instr.h91 V3D_QPU_WADDR_R0 = 0, enumerator in enum:v3d_qpu_waddr
H A Dqpu_instr.c33 [V3D_QPU_WADDR_R0] = "r0",
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_instr.c39 [V3D_QPU_WADDR_R0] = "r0",
885 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R0))
H A Dqpu_instr.h91 V3D_QPU_WADDR_R0 = 0, enumerator in enum:v3d_qpu_waddr

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