Searched refs:V3D_QPU_WADDR_R5 (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dvir_opt_copy_propagate.c74 case V3D_QPU_WADDR_R5:
H A Dvir_to_qpu.c104 src.index <= V3D_QPU_WADDR_R5);
279 dst.index != V3D_QPU_WADDR_R5) {
H A Dqpu_schedule.c230 case V3D_QPU_WADDR_R5:
H A Dnir_to_vir.c991 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dvir_opt_copy_propagate.c74 case V3D_QPU_WADDR_R5:
H A Dvir_to_qpu.c110 src.index <= V3D_QPU_WADDR_R5);
280 dst.index != V3D_QPU_WADDR_R5) {
H A Dqpu_schedule.c199 case V3D_QPU_WADDR_R5:
H A Dnir_to_vir.c576 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_instr.c38 [V3D_QPU_WADDR_R5] = "r5",
784 inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
789 inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {
795 inst->sig_magic && inst->sig_addr == V3D_QPU_WADDR_R5) {
H A Dqpu_instr.h96 V3D_QPU_WADDR_R5 = 5, enumerator in enum:v3d_qpu_waddr
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_instr.c44 [V3D_QPU_WADDR_R5] = "r5",
865 if (qpu_writes_magic_waddr_explicitly(devinfo, inst, V3D_QPU_WADDR_R5))
H A Dqpu_instr.h96 V3D_QPU_WADDR_R5 = 5, enumerator in enum:v3d_qpu_waddr

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