Searched refs:VE0_FORMAT_SHIFT (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c922 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
931 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
942 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
952 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1335 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1353 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1370 (src_format << VE0_FORMAT_SHIFT) |
1388 (src_format << VE0_FORMAT_SHIFT) |
H A Di810_reg.h2669 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_video.c1022 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1034 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1048 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1061 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1557 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1566 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1479 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1496 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1512 (src_format << VE0_FORMAT_SHIFT) |
1529 (src_format << VE0_FORMAT_SHIFT) |
2796 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2805 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2814 (src_format << VE0_FORMAT_SHIFT) |
2825 (src_format << VE0_FORMAT_SHIFT) |
H A Di965_reg.h355 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_video.c1023 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1035 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1049 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1062 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1558 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1567 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1479 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1496 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1512 (src_format << VE0_FORMAT_SHIFT) |
1529 (src_format << VE0_FORMAT_SHIFT) |
2796 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2805 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2814 (src_format << VE0_FORMAT_SHIFT) |
2825 (src_format << VE0_FORMAT_SHIFT) |
H A Di965_reg.h355 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h328 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h328 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen5_render.c968 (GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT) |
977 GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
992 format = GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT;
998 format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT;
1004 format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT;
1010 format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT;
1028 format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT;
1036 format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT;
1042 format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT;
H A Dgen4_render.c1025 GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
1066 src_format << VE0_FORMAT_SHIFT |
1099 src_format << VE0_FORMAT_SHIFT |
1104 GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
H A Dgen6_render.c837 GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
846 GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
885 src_format << VE0_FORMAT_SHIFT |
917 src_format << VE0_FORMAT_SHIFT |
H A Dgen6_render.h148 #define VE0_FORMAT_SHIFT 16 macro
H A Dgen4_render.h130 #define VE0_FORMAT_SHIFT 16 macro
H A Dgen5_render.h218 #define VE0_FORMAT_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen5_render.c931 (GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT) |
940 GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
955 format = GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT;
961 format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT;
967 format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT;
973 format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT;
991 format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT;
999 format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT;
1005 format = GEN5_SURFACEFORMAT_R32G32B32_FLOAT << VE0_FORMAT_SHIFT;
H A Dgen4_render.c988 GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
1029 src_format << VE0_FORMAT_SHIFT |
1062 src_format << VE0_FORMAT_SHIFT |
1067 GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
H A Dgen6_render.c803 GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
812 GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
851 src_format << VE0_FORMAT_SHIFT |
883 src_format << VE0_FORMAT_SHIFT |
H A Dgen6_render.h148 #define VE0_FORMAT_SHIFT 16 macro
H A Dgen4_render.h130 #define VE0_FORMAT_SHIFT 16 macro
H A Dgen5_render.h218 #define VE0_FORMAT_SHIFT 16 macro

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