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Searched refs:VE0_VALID (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A D	i965_video.c	`921 VE0_VALID \| 930 VE0_VALID \| 941 VE0_VALID \| 951 VE0_VALID \|`
H A D	i965_render.c	`1334 VE0_VALID \| 1352 VE0_VALID \| 1369 VE0_VALID \| 1387 VE0_VALID \|`
H A D	i810_reg.h	`2668 #define VE0_VALID (1 << 26) macro`
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A D	i965_reg.h	`353 #define VE0_VALID (1 << 26) macro`
H A D	i965_video.c	`1021 VE0_VALID \| 1033 VE0_VALID \| 1047 VE0_VALID \| 1060 VE0_VALID \|`
H A D	i965_render.c	`1478 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1495 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1511 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1528 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \|`
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A D	i965_reg.h	`326 #define VE0_VALID (1 << 26) macro`
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A D	i965_reg.h	`353 #define VE0_VALID (1 << 26) macro`
H A D	i965_video.c	`1022 VE0_VALID \| 1034 VE0_VALID \| 1048 VE0_VALID \| 1061 VE0_VALID \|`
H A D	i965_render.c	`1478 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1495 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1511 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 1528 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \|`
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A D	i965_reg.h	`326 #define VE0_VALID (1 << 26) macro`
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A D	gen4_render.c	`1024 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1065 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1098 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1103 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen5_render.c	`967 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 976 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1016 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1048 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen6_render.c	`836 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 845 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 884 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 916 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen6_render.h	`147 #define VE0_VALID (1 << 25) /* for GEN6 */ macro`
H A D	gen4_render.h	`129 #define VE0_VALID (1 << 26) macro`
H A D	gen5_render.h	`216 #define VE0_VALID (1 << 26) macro`
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A D	gen4_render.c	`987 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1028 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1061 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1066 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen5_render.c	`930 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) \| VE0_VALID \| 939 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 979 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 1011 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen6_render.c	`802 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 811 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 850 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \| 882 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT \| VE0_VALID \|`
H A D	gen6_render.h	`147 #define VE0_VALID (1 << 25) /* for GEN6 */ macro`
H A D	gen4_render.h	`129 #define VE0_VALID (1 << 26) macro`
H A D	gen5_render.h	`216 #define VE0_VALID (1 << 26) macro`

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