Searched refs:VE0_VERTEX_BUFFER_INDEX_SHIFT (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c920 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
929 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
940 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
950 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
H A Di965_render.c1333 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1351 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1368 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1386 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
H A Di810_reg.h2667 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_reg.h351 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
H A Di965_video.c1020 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1032 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1046 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1059 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
H A Di965_render.c1478 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1495 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1511 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1528 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h324 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_reg.h351 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
H A Di965_video.c1021 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1033 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1047 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1060 OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
H A Di965_render.c1478 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1495 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1511 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
1528 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h324 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.c1024 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1065 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1098 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1103 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen5_render.c967 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
976 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1016 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1048 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen6_render.c836 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
845 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
884 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
916 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen6_render.h146 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ macro
H A Dgen4_render.h128 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
H A Dgen5_render.h214 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.c987 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1028 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1061 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1066 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen5_render.c930 OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID |
939 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
979 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
1011 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen6_render.c802 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
811 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
850 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
882 OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
H A Dgen6_render.h146 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ macro
H A Dgen4_render.h128 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro
H A Dgen5_render.h214 #define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 macro

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