Searched refs:VE1_VFCOMPONENT_3_SHIFT (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_render.c1485 (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
1503 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1508 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1519 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1524 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1536 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1541 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
2801 (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
2810 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2819 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
[all...]
H A Di965_video.c1030 VE1_VFCOMPONENT_3_SHIFT));
1042 VE1_VFCOMPONENT_3_SHIFT));
1056 VE1_VFCOMPONENT_3_SHIFT) | (0 <<
1069 VE1_VFCOMPONENT_3_SHIFT) | (4 <<
1562 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1571 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
H A Di965_reg.h360 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_render.c1485 (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
1503 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1508 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1519 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1524 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1536 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1541 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
2801 (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
2810 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
2819 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
[all...]
H A Di965_video.c1031 VE1_VFCOMPONENT_3_SHIFT));
1043 VE1_VFCOMPONENT_3_SHIFT));
1057 VE1_VFCOMPONENT_3_SHIFT) | (0 <<
1070 VE1_VFCOMPONENT_3_SHIFT) | (4 <<
1563 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1572 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
H A Di965_reg.h360 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c927 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
936 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
947 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
957 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
H A Di965_render.c1341 (BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
1360 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1365 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1377 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1382 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1395 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
1400 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
H A Di810_reg.h2674 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h333 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h333 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.c1030 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT |
1036 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
1075 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
1109 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT |
H A Dgen5_render.c973 (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
982 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
987 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
1025 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
H A Dgen6_render.c842 GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
851 GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
855 dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
893 dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
H A Dgen6_render.h153 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
H A Dgen4_render.h135 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
H A Dgen5_render.h223 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.c993 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT |
999 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
1038 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
1072 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT |
H A Dgen5_render.c936 (VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT));
945 VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
950 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
988 dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
H A Dgen6_render.c808 GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
817 GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
821 dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
859 dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT;
H A Dgen6_render.h153 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
H A Dgen4_render.h135 #define VE1_VFCOMPONENT_3_SHIFT 16 macro
H A Dgen5_render.h223 #define VE1_VFCOMPONENT_3_SHIFT 16 macro

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