Searched refs:VR00 (Results 1 - 2 of 2) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/ivch/
H A Divch_reg.h38 /** @defgroup VR00 VCH Revision & GMBus Base Addr
41 #define VR00 0x00 macro
H A Divch.c181 if (!ivch_read(priv, VR00, &temp))
307 ivch_read(priv, VR00, &val);
308 xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR00: 0x%04x\n", val);

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