Searched refs:WRITEMASK_XYZ (Results 1 - 25 of 29) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/tests/
H A Dtest_glsl_to_tgsi_array_merge.cpp109 array_live_range a2(2, 9, 1, 10, WRITEMASK_XYZ);
139 array_live_range a1(1, 10, 1, 10, WRITEMASK_XYZ);
329 EXPECT_EQ(a3.access_mask(), WRITEMASK_XYZ);
682 {4, 4, 8, 9, WRITEMASK_XYZ},
905 { TGSI_OPCODE_MOV, {MT(4, 4, WRITEMASK_XYZ)}, {MT(0, in0, "xyz")}, {}, ARR()},
912 { TGSI_OPCODE_ADD, {MT(0, out1, WRITEMASK_XYZ)}, {MT(4, 4, "xyz"), MT(0, in0, "xyz")}, {}, ARR()},
923 { TGSI_OPCODE_MOV, {MT(1, 4, WRITEMASK_XYZ)}, {MT(0, in0, "xyz")}, {}, ARR()},
930 { TGSI_OPCODE_ADD, {MT(0, out1, WRITEMASK_XYZ)}, {MT(1, 4, "xyz"), MT(0, in0, "xyz")}, {}, ARR()},
/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/tests/
H A Dtest_glsl_to_tgsi_array_merge.cpp109 array_live_range a2(2, 9, 1, 10, WRITEMASK_XYZ);
139 array_live_range a1(1, 10, 1, 10, WRITEMASK_XYZ);
329 EXPECT_EQ(a3.access_mask(), WRITEMASK_XYZ);
682 {4, 4, 8, 9, WRITEMASK_XYZ},
905 { TGSI_OPCODE_MOV, {MT(4, 4, WRITEMASK_XYZ)}, {MT(0, in0, "xyz")}, {}, ARR()},
912 { TGSI_OPCODE_ADD, {MT(0, out1, WRITEMASK_XYZ)}, {MT(4, 4, "xyz"), MT(0, in0, "xyz")}, {}, ARR()},
923 { TGSI_OPCODE_MOV, {MT(1, 4, WRITEMASK_XYZ)}, {MT(0, in0, "xyz")}, {}, ARR()},
930 { TGSI_OPCODE_ADD, {MT(0, out1, WRITEMASK_XYZ)}, {MT(1, 4, "xyz"), MT(0, in0, "xyz")}, {}, ARR()},
/xsrc/external/mit/MesaLib.old/dist/src/mesa/program/
H A Dprog_instruction.h82 #define WRITEMASK_XYZ 0x7 macro
H A Dprogramopt.c381 inst->DstReg.WriteMask = WRITEMASK_XYZ;
H A Dprog_optimize.c95 channel_mask = WRITEMASK_XYZ;
H A Dprog_to_nir.c436 WRITEMASK_XYZ);
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dtest_vec4_copy_propagation.cpp164 v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
H A Dbrw_clip_util.c94 brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos,
H A Dbrw_vec4_visitor.cpp1076 emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), lod));
1077 emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), lod2));
1177 ndc_xyz.writemask = WRITEMASK_XYZ;
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dtest_vec4_copy_propagation.cpp175 v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
H A Dbrw_clip_util.c94 brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos,
H A Dbrw_vec4_visitor.cpp981 emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), lod));
982 emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), lod2));
1082 ndc_xyz.writemask = WRITEMASK_XYZ;
/xsrc/external/mit/MesaLib/dist/src/mesa/program/
H A Dprog_instruction.h82 #define WRITEMASK_XYZ 0x7 macro
H A Dprogramopt.c381 inst->DstReg.WriteMask = WRITEMASK_XYZ;
H A Dprog_optimize.c95 channel_mask = WRITEMASK_XYZ;
H A Dprog_to_nir.c414 WRITEMASK_XYZ);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/main/
H A Dffvertex_prog.c902 emit_op3(p, OPCODE_MAD, tmp, WRITEMASK_XYZ, lm_ambient,
1177 mask0 = WRITEMASK_XYZ;
1178 mask1 = WRITEMASK_XYZ;
1184 mask1 = WRITEMASK_XYZ;
1232 mask0 = WRITEMASK_XYZ;
1233 mask1 = WRITEMASK_XYZ;
1239 mask1 = WRITEMASK_XYZ;
H A Dff_fragment_shader.cpp680 p->emit(assign(temp_var, val, WRITEMASK_XYZ));
976 p->emit(assign(fog_result, add(temp, mul(fragcolor, f_var)), WRITEMASK_XYZ));
1024 WRITEMASK_XYZ));
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Dffvertex_prog.c911 emit_op3(p, OPCODE_MAD, tmp, WRITEMASK_XYZ, lm_ambient,
1240 mask0 = WRITEMASK_XYZ;
1241 mask1 = WRITEMASK_XYZ;
1247 mask1 = WRITEMASK_XYZ;
1307 mask0 = WRITEMASK_XYZ;
1308 mask1 = WRITEMASK_XYZ;
1314 mask1 = WRITEMASK_XYZ;
H A Dff_fragment_shader.cpp671 p->emit(assign(temp_var, val, WRITEMASK_XYZ));
965 p->emit(assign(fog_result, add(temp, mul(fragcolor, f_var)), WRITEMASK_XYZ));
1013 WRITEMASK_XYZ));
H A Datifragshader.c728 curI->DstReg[optype].dstMask = WRITEMASK_XYZ;
/xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
H A Dlower_blend_equation_advanced.cpp421 WRITEMASK_XYZ));
/xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
H A Dlower_blend_equation_advanced.cpp423 WRITEMASK_XYZ));
/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu.h58 #define WRITEMASK_XYZ (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu.h58 #define WRITEMASK_XYZ (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z) macro

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