| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | test_vec4_register_coalesce.cpp | 179 m0.writemask = WRITEMASK_Y;
190 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
203 to.writemask = WRITEMASK_Y;
216 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
229 to.writemask = WRITEMASK_Y;
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| H A D | brw_vec4_cmod_propagation.cpp | 166 scan_inst->dst.writemask == WRITEMASK_Y) ||
209 case WRITEMASK_Y:
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| H A D | brw_vec4_surface_builder.cpp | 203 bld.MOV(writemask(srcs, WRITEMASK_Y),
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| H A D | brw_vec4_visitor.cpp | 476 tmp_dst.writemask = WRITEMASK_Y;
1017 writemask = WRITEMASK_Y;
1048 emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
1066 emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), lod2));
1257 reg_y.writemask = WRITEMASK_Y;
1549 if (inst->dst.writemask & WRITEMASK_Y)
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| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | test_vec4_register_coalesce.cpp | 190 m0.writemask = WRITEMASK_Y;
201 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
214 to.writemask = WRITEMASK_Y;
227 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
240 to.writemask = WRITEMASK_Y;
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| H A D | brw_vec4_cmod_propagation.cpp | 166 scan_inst->dst.writemask == WRITEMASK_Y) ||
209 case WRITEMASK_Y:
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| H A D | brw_vec4_surface_builder.cpp | 201 bld.MOV(writemask(srcs, WRITEMASK_Y),
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| H A D | brw_vec4_visitor.cpp | 463 tmp_dst.writemask = WRITEMASK_Y;
931 writemask = WRITEMASK_Y;
953 emit(MOV(dst_reg(MRF, param_base + 1, glsl_type::uint_type, WRITEMASK_Y),
971 emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_Y), lod2));
1162 reg_y.writemask = WRITEMASK_Y;
1441 if (inst->dst.writemask & WRITEMASK_Y)
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| /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/ |
| H A D | lower_packing_builtins.cpp | 291 factory.emit(assign(u2, rshift(u, constant(16u)), WRITEMASK_Y));
324 WRITEMASK_Y));
356 WRITEMASK_Y));
364 constant(0xffu)), WRITEMASK_Y));
405 WRITEMASK_Y));
1061 WRITEMASK_Y));
1280 WRITEMASK_Y));
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| H A D | opt_vectorize.cpp | 227 case WRITEMASK_Y: return SWIZZLE_Y;
242 (write_mask == WRITEMASK_Y && swz->mask.x == SWIZZLE_Y) ||
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| H A D | ir_builder.h | 34 WRITEMASK_Y = 0x2, enumerator in enum:ir_builder::writemask
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| /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/ |
| H A D | lower_packing_builtins.cpp | 291 factory.emit(assign(u2, rshift(u, constant(16u)), WRITEMASK_Y));
324 WRITEMASK_Y));
356 WRITEMASK_Y));
364 constant(0xffu)), WRITEMASK_Y));
405 WRITEMASK_Y));
1061 WRITEMASK_Y));
1280 WRITEMASK_Y));
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| H A D | opt_vectorize.cpp | 227 case WRITEMASK_Y: return SWIZZLE_Y;
242 (write_mask == WRITEMASK_Y && swz->mask.x == SWIZZLE_Y) ||
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| H A D | ir_builder.h | 34 WRITEMASK_Y = 0x2, enumerator in enum:ir_builder::writemask
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/program/ |
| H A D | prog_instruction.c | 211 inst->DstReg.WriteMask == WRITEMASK_Y ||
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| H A D | prog_instruction.h | 77 #define WRITEMASK_Y 0x2 macro
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| H A D | program_lexer.l | 93 return WRITEMASK_Y;
368 yylval->swiz_mask.mask = WRITEMASK_Y
425 yylval->swiz_mask.mask = WRITEMASK_Y
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| H A D | prog_to_nir.c | 301 ptn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)), WRITEMASK_Y);
323 WRITEMASK_Y);
338 ptn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), WRITEMASK_Y);
355 nir_imm_float(b, 0.0)), WRITEMASK_Y);
394 WRITEMASK_Y);
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| /xsrc/external/mit/MesaLib/dist/src/mesa/program/ |
| H A D | prog_instruction.c | 213 inst->DstReg.WriteMask == WRITEMASK_Y ||
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| H A D | prog_instruction.h | 77 #define WRITEMASK_Y 0x2 macro
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| H A D | program_lexer.l | 93 return WRITEMASK_Y;
368 yylval->swiz_mask.mask = WRITEMASK_Y
425 yylval->swiz_mask.mask = WRITEMASK_Y
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| H A D | prog_to_nir.c | 301 ptn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)), WRITEMASK_Y);
323 WRITEMASK_Y);
338 ptn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), WRITEMASK_Y);
355 nir_imm_float(b, 0.0)), WRITEMASK_Y);
386 WRITEMASK_Y);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_liverange.cpp | 308 if (writemask & WRITEMASK_Y)
323 if (readmask & WRITEMASK_Y)
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| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| H A D | brw_eu.h | 53 #define WRITEMASK_Y 0x2 macro
57 #define WRITEMASK_XY (WRITEMASK_X | WRITEMASK_Y)
58 #define WRITEMASK_XYZ (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z)
59 #define WRITEMASK_XYZW (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z | WRITEMASK_W)
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| H A D | brw_eu.h | 53 #define WRITEMASK_Y 0x2 macro
57 #define WRITEMASK_XY (WRITEMASK_X | WRITEMASK_Y)
58 #define WRITEMASK_XYZ (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z)
59 #define WRITEMASK_XYZW (WRITEMASK_X | WRITEMASK_Y | WRITEMASK_Z | WRITEMASK_W)
|