Searched refs:WRITE_VID32 (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Dtv_geode.c35 WRITE_VID32(SC1400_TVOUT_HORZ_TIM, 0x00790359);
36 WRITE_VID32(SC1400_TVOUT_HORZ_SYNC, 0x03580350);
37 WRITE_VID32(SC1400_TVOUT_VERT_SYNC, 0x0A002001);
38 WRITE_VID32(SC1400_TVOUT_LINE_END, 0x039C00F0);
39 WRITE_VID32(SC1400_TVOUT_VERT_DOWNSCALE, 0xFFFFFFFF);
40 WRITE_VID32(SC1400_TVOUT_HORZ_SCALING, 0x10220700);
41 WRITE_VID32(SC1400_TVOUT_EMMA_BYPASS, 0x0002D0F0);
42 WRITE_VID32(SC1400_TVENC_TIM_CTRL_1, 0xA2E03000);
43 WRITE_VID32(SC1400_TVENC_TIM_CTRL_2, 0x1FF20000);
44 WRITE_VID32(SC1400_TVENC_TIM_CTRL_
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H A Dtv_1200.c215 WRITE_VID32(SC1200_TVOUT_HORZ_SYNC, 0x03580350);
220 WRITE_VID32(SC1200_TVOUT_VERT_SYNC, 0x05001000);
223 WRITE_VID32(SC1200_TVOUT_VERT_DOWNSCALE, 0xffffffff);
233 WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, 0xa2a01050);
239 WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, 0x9ff000f9 | ctrl2);
241 WRITE_VID32(SC1200_TVENC_SUB_FREQ, 0x21f07c1f);
243 WRITE_VID32(SC1200_TVENC_DISP_POS, 0x00120071);
245 WRITE_VID32(SC1200_TVENC_DISP_SIZE, 0x00ef02cf);
251 WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x00740359);
257 WRITE_VID32(SC1200_TVOUT_HORZ_SCALIN
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H A Dvid_1400.c126 WRITE_VID32(SC1400_VID_MISC, 0x00001000);
127 WRITE_VID32(SC1400_VID_CLOCK_SELECT, value);
172 WRITE_VID32(SC1400_VIDEO_CONFIG, vcfg);
177 WRITE_VID32(SC1400_VIDEO_CONFIG, vcfg);
212 WRITE_VID32(SC1400_VIDEO_CONFIG, vcfg);
242 WRITE_VID32(SC1400_VIDEO_CONFIG, vcfg);
315 WRITE_VID32(SC1400_VIDEO_SCALE, (yscale << 16) | xscale);
419 WRITE_VID32(SC1400_VIDEO_CONFIG, vcfg);
423 WRITE_VID32(SC1400_VIDEO_X_POS, (xend << 16) | xstart);
424 WRITE_VID32(SC1400_VIDEO_Y_PO
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H A Dvid_1200.c399 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
444 WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL);
445 WRITE_VID32(SC1200_VID_CLOCK_SELECT, value);
467 WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_DIS_EN);
469 WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~SC1200_DCFG_DIS_EN);
499 WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~(SC1200_DCFG_HSYNC_EN
502 WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN);
505 WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_HSYNC_EN
507 WRITE_VID32(SC1200_VID_MISC, misc & ~SC1200_DAC_POWER_DOWN);
513 WRITE_VID32(SC1200_DISPLAY_CONFI
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H A Dvid_5530.c328 WRITE_VID32(CS5530_DISPLAY_CONFIG,
336 WRITE_VID32(CS5530_DISPLAY_CONFIG,
344 WRITE_VID32(CS5530_DISPLAY_CONFIG,
353 WRITE_VID32(CS5530_DISPLAY_CONFIG,
436 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
479 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value);
480 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value | 0x80000100); /* set reset/bypass */
482 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFFFF); /* clear reset */
483 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFEFF); /* clear bypass */
528 WRITE_VID32(CS5530_VIDEO_CONFI
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H A Dvid_rdcl.c416 WRITE_VID32(RCDF_POWER_MANAGEMENT, power);
426 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
541 WRITE_VID32(RCDF_DISPLAY_CONFIG,
544 WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN);
549 WRITE_VID32(RCDF_DISPLAY_CONFIG,
552 WRITE_VID32(RCDF_VID_MISC,
558 WRITE_VID32(RCDF_DISPLAY_CONFIG,
562 WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN);
567 WRITE_VID32(RCDF_DISPLAY_CONFIG,
571 WRITE_VID32(RCDF_VID_MIS
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H A Dgfx_defs.h188 #define WRITE_VID32(offset, value) \ macro
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Dtv_1200.c60 WRITE_VID32(SC1200_TVOUT_HORZ_SYNC, 0x03580350);
65 WRITE_VID32(SC1200_TVOUT_VERT_SYNC, 0x05001000);
68 WRITE_VID32(SC1200_TVOUT_VERT_DOWNSCALE, 0xffffffff);
79 WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, 0xa2a01050);
85 WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, 0x9ff000f9 | ctrl2);
87 WRITE_VID32(SC1200_TVENC_SUB_FREQ, 0x21f07c1f);
89 WRITE_VID32(SC1200_TVENC_DISP_POS, 0x00120071);
91 WRITE_VID32(SC1200_TVENC_DISP_SIZE, 0x00ef02cf);
97 WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x00740359);
104 WRITE_VID32(SC1200_TVOUT_HORZ_SCALIN
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H A Dvid_1200.c240 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
285 WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL);
286 WRITE_VID32(SC1200_VID_CLOCK_SELECT, value);
309 WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_DIS_EN);
311 WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~SC1200_DCFG_DIS_EN);
341 WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~(SC1200_DCFG_HSYNC_EN
344 WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN);
348 WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_HSYNC_EN
350 WRITE_VID32(SC1200_VID_MISC, misc & ~SC1200_DAC_POWER_DOWN);
356 WRITE_VID32(SC1200_DISPLAY_CONFI
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H A Dvid_5530.c102 WRITE_VID32(CS5530_DISPLAY_CONFIG,
110 WRITE_VID32(CS5530_DISPLAY_CONFIG,
118 WRITE_VID32(CS5530_DISPLAY_CONFIG,
126 WRITE_VID32(CS5530_DISPLAY_CONFIG,
222 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
265 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value);
266 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value | 0x80000100);
269 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFFFF);
271 WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFEFF);
312 WRITE_VID32(CS5530_VIDEO_CONFI
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H A Dvid_rdcl.c218 WRITE_VID32(RCDF_POWER_MANAGEMENT, power);
227 WRITE_VID32(0x408, pt2);
235 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
352 WRITE_VID32(RCDF_DISPLAY_CONFIG,
355 WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN);
360 WRITE_VID32(RCDF_DISPLAY_CONFIG,
363 WRITE_VID32(RCDF_VID_MISC,
369 WRITE_VID32(RCDF_DISPLAY_CONFIG,
372 WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN);
377 WRITE_VID32(RCDF_DISPLAY_CONFI
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H A Dgfx_defs.h84 #define WRITE_VID32(offset, value) \ macro
/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_df.c87 WRITE_VID32(DF_DISPLAY_CONFIG, config);
88 WRITE_VID32(DF_VID_MISC, misc);
111 WRITE_VID32(DF_POWER_MANAGEMENT, pm);
151 WRITE_VID32(DF_VID_MISC, misc);
254 WRITE_VID32(DF_VIDEO_CONFIG, vcfg);
255 WRITE_VID32(DF_VID_ALPHA_CONTROL, ctrl);
256 WRITE_VID32(DF_VIDEO_SCALER, scale);
386 WRITE_VID32(DF_VIDEO_SCALER, scale | DF_SCALE_DOUBLE_H_DOWNSCALE);
389 WRITE_VID32(DF_VIDEO_SCALER, scale & ~DF_SCALE_DOUBLE_H_DOWNSCALE);
403 WRITE_VID32(DF_VIDEO_CONFI
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H A Dcim_vg.c546 WRITE_VID32(DF_POWER_MANAGEMENT, (temp | DF_PM_INVERT_SHFCLK));
550 WRITE_VID32(DF_POWER_MANAGEMENT, (temp & ~DF_PM_INVERT_SHFCLK));
580 WRITE_VID32(DF_VIDEO_PANEL_TIM1, pmtim1);
581 WRITE_VID32(DF_VIDEO_PANEL_TIM2, pmtim2);
582 WRITE_VID32(DF_DITHER_CONTROL, dith_ctl);
657 WRITE_VID32(DF_ALPHA_CONTROL_1, 0);
658 WRITE_VID32(DF_ALPHA_CONTROL_1 + 32, 0);
659 WRITE_VID32(DF_ALPHA_CONTROL_1 + 64, 0);
663 WRITE_VID32(DF_VIDEO_CONFIG, (temp & ~DF_VCFG_VID_EN));
699 WRITE_VID32(DF_VID_MIS
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H A Dcim_vop.c294 WRITE_VID32(DF_VID_ALPHA_CONTROL, alpha);
H A Dcim_defs.h67 #define WRITE_VID32(offset, value) \ macro
/xsrc/external/mit/xf86-video-nsc/dist/src/panel/
H A Dpnl_init.c320 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
328 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
336 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
384 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
392 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
400 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
H A Ddora9211.c334 WRITE_VID32(0x04, 0x00200141);
342 WRITE_VID32(0X4, orig_value);
/xsrc/external/mit/xf86-video-geode/dist/src/panel/
H A Dpnl_init.c223 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
232 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
241 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
291 WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg);
300 WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
309 WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg);
H A Ddora9211.c226 WRITE_VID32(0x04, 0x00200141);
234 WRITE_VID32(0X4, orig_value);
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_gx1_driver.c1509 WRITE_VID32(SC1200_TVOUT_HORZ_TIM, pGeode->FBtvtiming.HorzTim);
1510 WRITE_VID32(SC1200_TVOUT_HORZ_SYNC, pGeode->FBtvtiming.HorzSync);
1511 WRITE_VID32(SC1200_TVOUT_VERT_SYNC, pGeode->FBtvtiming.VertSync);
1512 WRITE_VID32(SC1200_TVOUT_LINE_END, pGeode->FBtvtiming.LineEnd);
1513 WRITE_VID32(SC1200_TVOUT_VERT_DOWNSCALE,
1515 WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, pGeode->FBtvtiming.HorzScaling);
1516 WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, pGeode->FBtvtiming.TimCtrl1);
1517 WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, pGeode->FBtvtiming.TimCtrl2);
1518 WRITE_VID32(SC1200_TVENC_SUB_FREQ, pGeode->FBtvtiming.Subfreq);
1519 WRITE_VID32(SC1200_TVENC_DISP_PO
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H A Dnsc_regacc.c205 WRITE_VID32(offset, value);
/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dgx_regacc.c117 WRITE_VID32(offset, value);
H A Dlx_display.c57 WRITE_VID32(DF_VID_MISC, misc);
379 WRITE_VID32(DF_DISPLAY_CONFIG, dcfg);
H A Dlx_video.c612 WRITE_VID32(DF_VID_MISC, val | DF_GAMMA_BYPASS_BOTH);
672 WRITE_VID32(DF_VID_MISC, val | DF_GAMMA_BYPASS_BOTH);

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