Searched refs:__u32 (Results 1 - 25 of 58) sorted by relevance

123

/xsrc/external/mit/MesaLib.old/dist/include/drm-uapi/
H A Dv3d_drm.h77 __u32 bcl_start;
80 __u32 bcl_end;
93 __u32 rcl_start;
96 __u32 rcl_end;
99 __u32 in_sync_bcl;
101 __u32 in_sync_rcl;
103 __u32 out_sync;
110 __u32 qma;
113 __u32 qms;
116 __u32 qt
[all...]
H A Dtegra_drm.h57 __u32 flags;
65 __u32 handle;
77 __u32 handle;
84 __u32 pad;
104 __u32 id;
112 __u32 value;
124 __u32 id;
131 __u32 pad;
143 __u32 id;
150 __u32 thres
[all...]
H A Dlima_drm.h30 __u32 param; /* in, value in enum drm_lima_param */
31 __u32 pad; /* pad, must be zero */
39 __u32 size; /* in, buffer size */
40 __u32 flags; /* in, currently no flags, must be zero */
41 __u32 handle; /* out, GEM buffer handle */
42 __u32 pad; /* pad, must be zero */
49 __u32 handle; /* in, GEM buffer handle */
50 __u32 va; /* out, virtual address mapped into GPU MMU */
59 __u32 handle; /* in, GEM buffer handle */
60 __u32 flag
[all...]
H A Ddrm_mode.h214 __u32 clock;
226 __u32 vrefresh;
228 __u32 flags;
229 __u32 type;
238 __u32 count_fbs;
239 __u32 count_crtcs;
240 __u32 count_connectors;
241 __u32 count_encoders;
242 __u32 min_width;
243 __u32 max_widt
[all...]
H A Dvc4_drm.h66 __u32 hindex; /* Handle index, or ~0 if not present. */
67 __u32 offset; /* Offset to start of buffer. */
117 * uniform data has a __u32 index into bo_handles per texture
130 __u32 bin_cl_size;
132 __u32 shader_rec_size;
139 __u32 shader_rec_count;
141 __u32 uniforms_size;
144 __u32 bo_handle_count;
159 __u32 clear_color[2];
160 __u32 clear_
[all...]
H A Dpanfrost_drm.h45 __u32 in_sync_count;
48 __u32 out_sync;
54 __u32 bo_handle_count;
57 __u32 requirements;
69 __u32 handle;
70 __u32 pad;
81 __u32 size;
82 __u32 flags;
84 __u32 handle;
109 __u32 handl
[all...]
/xsrc/external/mit/libdrm/dist/include/drm/
H A Dtegra_drm.h40 __u32 flags;
48 __u32 handle;
60 __u32 handle;
67 __u32 pad;
87 __u32 id;
95 __u32 value;
107 __u32 id;
114 __u32 pad;
126 __u32 id;
133 __u32 thres
[all...]
H A Dvirtgpu_drm.h59 __u32 handle;
60 __u32 pad;
64 __u32 flags;
65 __u32 size;
68 __u32 num_bo_handles;
83 __u32 target;
84 __u32 format;
85 __u32 bind;
86 __u32 width;
87 __u32 heigh
[all...]
H A Dvmwgfx_drm.h118 __u32 param;
119 __u32 pad64;
141 __u32 pad64;
183 __u32 flags;
184 __u32 format;
185 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
219 __u32 width;
220 __u32 height;
221 __u32 depth;
222 __u32 pad6
[all...]
H A Dqxl_drm.h54 __u32 size;
55 __u32 handle; /* 0 is an invalid handle */
60 __u32 handle;
61 __u32 pad;
76 __u32 src_handle; /* dest handle to compute address from */
77 __u32 dst_handle; /* 0 if to command buffer */
78 __u32 reloc_type;
79 __u32 pad;
85 __u32 type;
86 __u32 command_siz
[all...]
H A Ddrm_mode.h243 __u32 clock;
255 __u32 vrefresh;
257 __u32 flags;
258 __u32 type;
267 __u32 count_fbs;
268 __u32 count_crtcs;
269 __u32 count_connectors;
270 __u32 count_encoders;
271 __u32 min_width;
272 __u32 max_widt
[all...]
H A Damdgpu_drm.h188 __u32 handle;
189 __u32 _pad;
206 __u32 operation;
208 __u32 list_handle;
210 __u32 bo_number;
212 __u32 bo_info_size;
219 __u32 bo_handle;
221 __u32 bo_priority;
226 __u32 list_handle;
227 __u32 _pa
[all...]
H A Dvc4_drm.h66 __u32 hindex; /* Handle index, or ~0 if not present. */
67 __u32 offset; /* Offset to start of buffer. */
117 * uniform data has a __u32 index into bo_handles per texture
130 __u32 bin_cl_size;
132 __u32 shader_rec_size;
139 __u32 shader_rec_count;
141 __u32 uniforms_size;
144 __u32 bo_handle_count;
159 __u32 clear_color[2];
160 __u32 clear_
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/svga/drm/
H A Dvmwgfx_drm.h134 __u32 param;
135 __u32 pad64;
157 __u32 pad64;
199 __u32 flags;
200 __u32 format;
201 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
235 __u32 width;
236 __u32 height;
237 __u32 depth;
238 __u32 pad6
[all...]
/xsrc/external/mit/MesaLib/dist/include/drm-uapi/
H A Dvirtgpu_drm.h63 __u32 handle;
64 __u32 pad;
68 __u32 flags;
69 __u32 size;
72 __u32 num_bo_handles;
74 __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
75 __u32 pad;
94 __u32 target;
95 __u32 format;
96 __u32 bin
[all...]
H A Dtegra_drm.h57 __u32 flags;
65 __u32 handle;
77 __u32 handle;
84 __u32 pad;
104 __u32 id;
112 __u32 value;
124 __u32 id;
131 __u32 pad;
143 __u32 id;
150 __u32 thres
[all...]
H A Dlima_drm.h30 __u32 param; /* in, value in enum drm_lima_param */
31 __u32 pad; /* pad, must be zero */
46 __u32 size; /* in, buffer size */
47 __u32 flags; /* in, buffer flags */
48 __u32 handle; /* out, GEM buffer handle */
49 __u32 pad; /* pad, must be zero */
56 __u32 handle; /* in, GEM buffer handle */
57 __u32 va; /* out, virtual address mapped into GPU MMU */
66 __u32 handle; /* in, GEM buffer handle */
67 __u32 flag
[all...]
H A Ddrm_mode.h243 __u32 clock;
255 __u32 vrefresh;
257 __u32 flags;
258 __u32 type;
267 __u32 count_fbs;
268 __u32 count_crtcs;
269 __u32 count_connectors;
270 __u32 count_encoders;
271 __u32 min_width;
272 __u32 max_widt
[all...]
H A Dv3d_drm.h90 __u32 bcl_start;
93 __u32 bcl_end;
106 __u32 rcl_start;
109 __u32 rcl_end;
112 __u32 in_sync_bcl;
114 __u32 in_sync_rcl;
116 __u32 out_sync;
123 __u32 qma;
126 __u32 qms;
129 __u32 qt
[all...]
H A Damdgpu_drm.h157 __u32 handle;
158 __u32 _pad;
175 __u32 operation;
177 __u32 list_handle;
179 __u32 bo_number;
181 __u32 bo_info_size;
188 __u32 bo_handle;
190 __u32 bo_priority;
195 __u32 list_handle;
196 __u32 _pa
[all...]
H A Dvc4_drm.h66 __u32 hindex; /* Handle index, or ~0 if not present. */
67 __u32 offset; /* Offset to start of buffer. */
117 * uniform data has a __u32 index into bo_handles per texture
130 __u32 bin_cl_size;
132 __u32 shader_rec_size;
139 __u32 shader_rec_count;
141 __u32 uniforms_size;
144 __u32 bo_handle_count;
159 __u32 clear_color[2];
160 __u32 clear_
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/svga/drm/
H A Dvmwgfx_drm.h126 __u32 param;
127 __u32 pad64;
149 __u32 pad64;
191 __u32 flags;
192 __u32 format;
193 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
227 __u32 width;
228 __u32 height;
229 __u32 depth;
230 __u32 pad6
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/drm/
H A Dmsm_drm.h81 __u32 pipe; /* in, MSM_PIPE_x */
82 __u32 param; /* in, MSM_PARAM_x */
106 __u32 flags; /* in, mask of MSM_BO_x */
107 __u32 handle; /* out */
123 __u32 handle; /* in */
124 __u32 info; /* in - one of MSM_INFO_* */
126 __u32 len; /* in or out */
127 __u32 pad;
137 __u32 handle; /* in */
138 __u32 o
[all...]
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/fbdevhw/
H A Dfbpriv.h96 __u32 smem_len; /* Length of frame buffer mem */
97 __u32 type; /* see FB_TYPE_* */
98 __u32 type_aux; /* Interleave for interleaved Planes */
99 __u32 visual; /* see FB_VISUAL_* */
103 __u32 line_length; /* length of a line in bytes */
106 __u32 mmio_len; /* Length of Memory Mapped I/O */
107 __u32 accel; /* Type of acceleration available */
118 __u32 offset; /* beginning of bitfield */
119 __u32 length; /* length of bitfield */
120 __u32 msb_righ
[all...]
/xsrc/external/mit/xorg-server/dist/hw/xfree86/fbdevhw/
H A Dfbpriv.h96 __u32 smem_len; /* Length of frame buffer mem */
97 __u32 type; /* see FB_TYPE_* */
98 __u32 type_aux; /* Interleave for interleaved Planes */
99 __u32 visual; /* see FB_VISUAL_* */
103 __u32 line_length; /* length of a line in bytes */
106 __u32 mmio_len; /* Length of Memory Mapped I/O */
107 __u32 accel; /* Type of acceleration available */
118 __u32 offset; /* beginning of bitfield */
119 __u32 length; /* length of bitfield */
120 __u32 msb_righ
[all...]

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