Searched refs:a3xx (Results 1 - 25 of 31) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D9.2.4.rst59 - freedreno/a3xx: fix color inversion on mem->gmem restore
60 - freedreno/a3xx: fix viewport on gmem->mem resolve
63 - freedreno/a3xx: some texture fixes
64 - freedreno/a3xx/compiler: fix CMP
65 - freedreno/a3xx/compiler: handle saturate on dst
66 - freedreno/a3xx/compiler: use max_reg rather than file_count
67 - freedreno/a3xx/compiler: cat4 cannot use const reg as src
69 - freedreno/a3xx/compiler: make compiler errors more useful
70 - freedreno/a3xx/compiler: bit of re-arrange/cleanup
71 - freedreno/a3xx/compile
[all...]
H A D10.3.3.rst128 - freedreno/a3xx: enable hw primitive-restart
129 - freedreno/a3xx: handle rendering to layer != 0
131 - freedreno/a3xx: format fixes
133 - freedreno/a3xx: alpha render-target shenanigans
138 - freedreno/a3xx: 3d/array textures
140 - freedreno/a3xx: more texture array fixes
141 - freedreno/a3xx: initial texture border-color
147 - freedreno/a3xx: add LOD_BIAS
148 - freedreno/a3xx: add flat interpolation mode
149 - freedreno/a3xx
[all...]
H A D10.2.3.rst74 - freedreno/a3xx: fix depth/stencil GMEM positioning
75 - freedreno/a3xx: fix depth/stencil gmem restore
76 - freedreno/a3xx: fix blend opcode
78 - freedreno/a3xx: texture fixes
80 - freedreno/a3xx: vtx formats
H A D10.5.3.rst74 - freedreno/a3xx: fix 3d texture layout
75 - freedreno/a3xx: point size should not be divided by 2
H A D10.3.5.rst61 - freedreno/a3xx: only enable blend clamp for non-float formats
H A D12.0.4.rst134 - a3xx: make sure to actually clamp depth as requested
135 - a3xx: make use of software clipping when hw can't handle it
136 - a3xx: use window scissor to simulate viewport xy clip
H A D10.5.2.rst72 - freedreno/a3xx: use the same layer size for all slices
H A D11.0.1.rst80 - freedreno/a3xx: fix blending of L8 format
H A D11.1.0.rst28 - OpenGL 3.1 support on freedreno (a3xx, a4xx)
33 - GL_ARB_blend_func_extended on freedreno (a3xx)
48 - GL_ARB_texture_buffer_range on freedreno/a3xx
52 - GL_ARB_vertex_type_2_10_10_10_rev on freedreno (a3xx, a4xx)
57 - GL_EXT_texture_compression_rgtc / latc on freedreno (a3xx & a4xx)
H A D11.0.0.rst31 - OpenGL ES 3.0 on freedreno (a3xx, a4xx)
49 GL_EXT_transform_feedback on a3xx, a4xx
53 - GL_EXT_texture_compression_s3tc on freedreno (a3xx)
H A D11.0.4.rst138 - freedreno/a3xx: cache-flush is needed after MEM_WRITE
H A D17.0.6.rst145 - freedreno/a3xx: fix hang w/ large render targets and small gmem
H A D20.1.3.rst153 - freedreno/a3xx: there's no r8i/ui rb format, only rg8i/rg8ui
154 - freedreno/a3xx: reinstate rgb10_a2ui texture format
H A D20.2.0.rst1650 - freedreno/ir3: Set up the block predecessors for a3xx TF
1651 - freedreno/ir3: Fix the a3xx TF outputs stores.
1721 - ci: Enable a fractional run with UBO-to-constbuf disabled on a3xx.
2426 - freedreno/a3xx: there's no r8i/ui rb format, only rg8i/rg8ui
2427 - freedreno/a3xx: reinstate rgb10_a2ui texture format
2429 - freedreno/a3xx: fix const footprint
2431 - freedreno/a3xx: parameterize ubo optimization
2432 - freedreno/a3xx: fix rasterizer discard
2792 - freedreno/a3xx: support LINEAR_PIXEL/PERSP_CENTROID/LINEAR_CENTROID sysvals
4137 - freedreno/a3xx
[all...]
H A D21.1.0.rst1319 - freedreno/a3xx: Fix SP_FS_CTRL_REG1_INITIALOUTSTANDING
1722 - ci/freedreno: Fix up the xfail/flake handling of a3xx texture functions.
1723 - ci/freedreno: Remove a bunch of stale flakes from a3xx.
1784 - ci/freedreno: Run a3xx gles3 in parallel and increase coverage.
1843 - ci/a3xx: Run all of GLES3 dEQP.
1880 - freedreno/a3xx: Switch to using ir3_cache for looking up our VS/FS.
1903 - ci/freedreno: Add trace testing on a3xx, a5xx.
H A D19.3.0.rst1122 - freedreno/a3xx: Mostly fix min-vs-mag filtering decisions on
2154 - freedreno/a3xx: fix texture tiling parameters
2155 - freedreno/a3xx: fix sysmem <-> gmem tiles transfer
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/
H A DMakefile.sources81 a3xx/fd3_blend.c \
82 a3xx/fd3_blend.h \
83 a3xx/fd3_context.c \
84 a3xx/fd3_context.h \
85 a3xx/fd3_draw.c \
86 a3xx/fd3_draw.h \
87 a3xx/fd3_emit.c \
88 a3xx/fd3_emit.h \
89 a3xx/fd3_format.c \
90 a3xx/fd3_forma
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/
H A DMakefile.sources19 ir3/disasm-a3xx.c \
20 ir3/instr-a3xx.h \
56 registers/a3xx.xml.h \
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/
H A Ddistro.rst59 Driver for Qualcomm Adreno a2xx, a3xx, and a4xx series of GPUs.
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/
H A Dir3-notes.rst4 Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with adreno a3xx. The same shader ISA is present, with some small differences, in adreno a4xx.
6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or nops). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
17 For additional documentation about the hardware, see wiki: `a3xx ISA
386 In this stage, simple if/else blocks are flattened into a single block with ``phi`` nodes converted into ``sel`` instructions. The a3xx ISA has very few predicated instructions, and we would prefer not to use branches for simple if/else.
/xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/
H A Dir3-notes.rst4 Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with adreno a3xx. The same shader ISA is present, with some small differences, in adreno a4xx.
6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
17 For additional documentation about the hardware, see wiki: `a3xx ISA
357 In this stage, simple if/else blocks are flattened into a single block with ``phi`` nodes converted into ``sel`` instructions. The a3xx ISA has very few predicated instructions, and we would prefer not to use branches for simple if/else.
/xsrc/external/mit/MesaLib/dist/docs/gallium/
H A Ddistro.rst59 Driver for Qualcomm Adreno a2xx, a3xx, and a4xx series of GPUs.
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dinstr-a3xx.h299 } a3xx; member in union:PACKED::PACKED
H A Ddisasm-a3xx.c33 #include "instr-a3xx.h"
92 // by libllvm-a3xx for easy diffing..
108 * libllvm-a3xx...
174 component[cat0->comp], cat0->a3xx.immed);
178 fprintf(ctx->out, " #%d", cat0->a3xx.immed);
227 * libllvm-a3xx...
1050 * try to match the order in llvm-a3xx disassembler for easy
H A Dir3.c37 #include "instr-a3xx.h"
146 cat0->a3xx.immed = instr->cat0.immed;
880 * instructions on a4xx or sets of 4 instructions on a3xx),

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