Searched refs:a6xx (Results 1 - 25 of 47) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/
H A DMakefile.sources168 a6xx/fd6_blend.c \
169 a6xx/fd6_blend.h \
170 a6xx/fd6_blitter.c \
171 a6xx/fd6_blitter.h \
172 a6xx/fd6_compute.c \
173 a6xx/fd6_compute.h \
174 a6xx/fd6_context.c \
175 a6xx/fd6_context.h \
176 a6xx/fd6_draw.c \
177 a6xx/fd6_dra
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/xsrc/external/mit/MesaLib/dist/src/freedreno/common/
H A Dfreedreno_devices.py107 """The a6xx generation has a lot more parameters, and is broken down
126 self.a6xx = Struct()
127 self.a6xx.magic = Struct()
130 setattr(self.a6xx.magic, name, val)
133 self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
134 self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
138 self.a6xx.has_cp_reg_write = True
139 self.a6xx.has_8bpp_ubwc = True
144 setattr(self.a6xx, name, val)
201 # a6xx ca
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H A Dfreedreno_dev_info.h75 /* newer a6xx allows using 16-bit descriptor for both 16-bit
101 /* The firmware on newer a6xx drops CP_REG_WRITE support as we
130 } a6xx; member in union:fd_dev_info::__anonb62ae096020a
140 * Note that gpu-id should be considered deprecated. For newer a6xx, if
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_compiler.c100 /* a6xx split the pipeline state into geometry and fragment state, in
128 fd_dev_info(compiler->dev_id)->a6xx.tess_use_shared;
131 fd_dev_info(compiler->dev_id)->a6xx.storage_16bit;
146 fd_dev_info(compiler->dev_id)->a6xx.reg_size_vec4;
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_nir_lower_multiview.c9 /* Some a6xx variants cannot support a non-contiguous multiview mask. Instead,
81 if (!dev->physical_device->info->a6xx.supports_multiview_mask)
91 dev->physical_device->info->a6xx.supports_multiview_mask ? 16 : 10;
H A Dtu_image.c470 if (!info->a6xx.has_8bpp_ubwc &&
506 if (!info->a6xx.has_z24uint_s8uint &&
511 if (!info->a6xx.has_z24uint_s8uint && samples > VK_SAMPLE_COUNT_1_BIT)
824 tu_image_view_init(view, pCreateInfo, device->physical_device->info->a6xx.has_z24uint_s8uint);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_rasterizer.c97 if (ctx->screen->info->a6xx.has_shading_rate) {
H A Dfd6_compute.c78 if (ctx->screen->info->a6xx.has_lpac) {
97 if (ctx->screen->info->a6xx.has_lpac) {
H A Dfd6_resource.c33 #include "a6xx.xml.h"
52 return info->a6xx.has_z24uint_s8uint;
91 return info->a6xx.has_8bpp_ubwc;
H A Dfd6_image.c149 enum pipe_format format = dev_info->a6xx.storage_16bit
170 unsigned sz = pimg->buffer_size / (dev_info->a6xx.storage_16bit ? 2 : 4);
H A Dfd6_gmem.c175 // XXX a6xx seems to use a different buffer here.. not sure
365 if (screen->info->a6xx.has_cp_reg_write) {
695 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
698 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
748 .unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
816 .unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
851 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
854 OUT_RING(ring, screen->info->a6xx.magic.PC_POWER_CNTL);
H A Dfd6_blitter.c416 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
511 OUT_RING(ring, batch->ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
689 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
817 OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
1069 if (!ctx->screen->info->a6xx.has_z24uint_s8uint) {
H A Dfd6_program.c106 uint32_t fibers_per_sp = ctx->screen->info->a6xx.fibers_per_sp;
164 if (ctx->screen->info->a6xx.tess_use_shared)
176 if (ctx->screen->info->a6xx.tess_use_shared) {
236 if (ctx->screen->info->a6xx.tess_use_shared)
264 if (ctx->screen->info->a6xx.tess_use_shared) {
678 if (ctx->screen->info->a6xx.tess_use_shared) {
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.2.4.rst51 - freedreno/a6xx: Fix typo in height alignment calculation in a6xx layout
H A D20.3.2.rst64 - freedreno/a6xx: Fix assert which checks the count of shader outputs
84 - freedreno/a6xx: Flush depth at the end of bypass rendering, too.
H A D20.2.0.rst131 - freedreno/a6xx: incorrect rendering in asphalt 9
145 - freedreno/a6xx: skai/skqp fails
192 - freedreno/a6xx: broken rendering in playcanvas "after the flood"
208 - freedreno/a6xx: gpu hangs in google earth
222 - freedreno: minetest: alpha channel issue on a6xx
271 - freedreno/a6xx: pubg rendering glitches
1020 - ir3: Unconditionally enable MERGEDREGS on a6xx
1139 - freedreno/a6xx: Document dual-src blending enable bits
1174 - freedreno/a6xx: use firstIndex field
1181 - freedreno/a6xx
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H A D20.0.0.rst701 - a6xx: Add more CP packets
1045 - freedreno/a6xx: Log the tiling mode in resource layout debug.
1065 - freedreno: Move a6xx's setup_slices() to a shareable helper function.
1099 - freedreno: Add some missing a6xx address declarations.
1814 - freedreno/registers: add a6xx texture format for stencil sampler
1995 - freedreno/a6xx: Fix primitive counters again
1996 - freedreno/a6xx: Clear sysmem with CP_BLIT
1998 - freedreno/a6xx: Fix layered texture type enum
2000 - freedreno/a6xx: Add register offset for STG/LDG
2016 - freedreno/a6xx
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H A D19.1.0.rst1290 - freedreno/a6xx: Silence compiler warnings
1760 - freedreno/a6xx: UBWC support
1762 - freedreno/a6xx: Enable UBWC modifier
3415 - freedreno/a6xx: Emit blitter dst with OUT_RELOCW
3416 - freedreno/a6xx: Use tiling for all resources
3417 - freedreno/a6xx: regen headers
3418 - freedreno/a6xx: Drop render condition check in blitter
3420 - freedreno/a6xx: Use the right resource for separate stencil stride
3421 - freedreno/a6xx: Combine emit_blit and fd6_blit
3424 - freedreno/a6xx
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H A D19.0.6.rst104 - freedreno/a6xx: fix GPU crash on small render targets
H A D19.1.1.rst115 - freedreno/a6xx: un-swap X24S8_UINT
H A D21.3.0.rst886 - tu, freedreno/a6xx, ir3: Rewrite tess PrimID handling
887 - tu, freedreno/a6xx: Fix setting PC_XS_OUT_CNTL::PRIMITVE_ID
890 - freedreno/a6xx: Add new register fields
893 - freedreno/a6xx: Document GRAS_SC_CNTL::SINGLE_PRIM_MODE
931 - freedreno/a6xx: Fix VS primid with tess + GS.
935 - freedreno/a6xx: Name TPL1_DBG_ECO_CNTL
1056 - ir3/a6xx,freedreno: account for resinfo return size dependency on IBO_0_FMT
1078 - tu: fix rast state allocation size on a6xx gen4
1327 - freedreno/a6xx: Apply the cube image size lowering to GL, too.
1330 - freedreno/ir3: Move a6xx'
[all...]
H A D18.3.4.rst111 - freedreno/a6xx: Emit blitter dst with OUT_RELOCW
H A D19.0.0.rst1634 - freedreno/a6xx: Clear z32 and separate stencil with blitter
1635 - freedreno/a6xx: Move restore blits to IB
1636 - freedreno/a6xx: Move resolve blits to an IB
1637 - freedreno/a6xx: Clear gmem buffers at flush time
1646 - freedreno/a6xx: Turn on texture tiling by default
1647 - freedreno/a6xx: Emit blitter dst with OUT_RELOCW
2089 - freedreno/a6xx: fix VSC bug with larger # of tiles
2107 - freedreno/a6xx: disable LRZ for z32
2108 - freedreno/a6xx: set guardband clip
2111 - freedreno/a6xx
[all...]
H A D20.0.2.rst129 - freedreno: android: add a6xx-pack.xml.h generation to android build
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/
H A DMakefile.sources59 registers/a6xx.xml.h \

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