Searched refs:array_mode (Results 1 - 25 of 37) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h106 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T
138 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/chip/r800/
H A Dsi_gb_reg.h106 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T
141 unsigned int array_mode : 4; member in struct:_GB_TILE_MODE_T
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Devergreen_accel.c208 unsigned pitch, slice, w, h, array_mode, nbanks; local in function:evergreen_set_render_target
216 array_mode = 2;
219 array_mode = 4;
222 array_mode = 0;
243 array_mode = cb_conf->array_mode;
260 (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
699 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local in function:evergreen_set_tex_resource
705 array_mode = 2;
708 array_mode
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H A Dr6xx_accel.c226 unsigned pitch, slice, h, array_mode; local in function:r600_set_render_target
234 array_mode = 2;
237 array_mode = 4;
240 array_mode = 0;
248 array_mode = cb_conf->array_mode;
256 (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
626 uint32_t array_mode, pitch; local in function:r600_set_tex_resource
632 array_mode = 2;
635 array_mode
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H A Devergreen_textured_videofuncs.c266 tex_res.array_mode = 1;
299 tex_res.array_mode = 1;
322 tex_res.array_mode = 1;
362 tex_res.array_mode = 1;
417 cb_conf.array_mode = 1;
H A Devergreen_state.h73 int array_mode; // tiling member in struct:__anon0a2b7a930208
158 int array_mode; member in struct:__anon0a2b7a930608
H A Dr600_state.h40 int array_mode; // tiling member in struct:__anonbd842b780208
71 int array_mode; // tiling member in struct:__anonbd842b780308
H A Devergreen_exa.c164 cb_conf.array_mode = 0;
343 tex_res.array_mode = 0;
386 cb_conf.array_mode = 0;
1006 tex_res.array_mode = 0;
1329 cb_conf.array_mode = 0;
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Devergreen_accel.c205 unsigned pitch, slice, w, h, array_mode, nbanks; local in function:evergreen_set_render_target
212 array_mode = 2;
215 array_mode = 4;
218 array_mode = 0;
237 array_mode = cb_conf->array_mode;
254 (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
691 uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks; local in function:evergreen_set_tex_resource
696 array_mode = 2;
699 array_mode
[all...]
H A Dr6xx_accel.c195 unsigned pitch, slice, h, array_mode; local in function:r600_set_render_target
202 array_mode = 2;
205 array_mode = 4;
208 array_mode = 0;
215 array_mode = cb_conf->array_mode;
223 (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
557 uint32_t array_mode, pitch; local in function:r600_set_tex_resource
562 array_mode = 2;
565 array_mode
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H A Devergreen_textured_videofuncs.c251 tex_res.array_mode = 1;
285 tex_res.array_mode = 1;
309 tex_res.array_mode = 1;
350 tex_res.array_mode = 1;
406 cb_conf.array_mode = 1;
H A Devergreen_state.h73 int array_mode; // tiling member in struct:__anon924f4acb0208
156 int array_mode; member in struct:__anon924f4acb0608
H A Dr600_state.h40 int array_mode; // tiling member in struct:__anonad3ef8b00208
69 int array_mode; // tiling member in struct:__anonad3ef8b00308
H A Devergreen_exa.c161 cb_conf.array_mode = 0;
341 tex_res.array_mode = 0;
385 cb_conf.array_mode = 0;
1023 tex_res.array_mode = 0;
1476 cb_conf.array_mode = 0;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_dma.c107 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; local in function:si_dma_copy_tile
129 array_mode = G_009910_ARRAY_MODE(tile_mode);
165 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
H A Dsi_texture.c224 enum radeon_surf_mode array_mode,
254 array_mode == RADEON_SURF_MODE_2D)) {
311 array_mode, surface);
342 enum radeon_surf_mode *array_mode,
347 *array_mode = RADEON_SURF_MODE_2D;
349 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
369 *array_mode = RADEON_SURF_MODE_2D;
371 *array_mode = RADEON_SURF_MODE_1D;
373 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1619 enum radeon_surf_mode array_mode; local in function:si_texture_from_winsys_buffer
221 si_init_surface(struct si_screen * sscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth,bool tc_compatible_htile) argument
339 si_get_display_metadata(struct si_screen * sscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout) argument
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_texture.c199 enum radeon_surf_mode array_mode,
249 flags, bpe, array_mode, surface);
297 enum radeon_surf_mode *array_mode,
308 *array_mode = RADEON_SURF_MODE_2D;
310 *array_mode = RADEON_SURF_MODE_1D;
312 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1122 enum radeon_surf_mode array_mode; local in function:r600_texture_from_handle
1142 &array_mode, &is_scanout);
1144 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
1918 enum radeon_surf_mode array_mode; local in function:r600_texture_from_memobj
196 r600_init_surface(struct r600_common_screen * rscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth) argument
294 r600_surface_import_metadata(struct r600_common_screen * rscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout) argument
[all...]
H A Dr600_state.c672 unsigned char swizzle[4], array_mode = 0; local in function:r600_create_sampler_view_custom
741 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
744 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
747 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
753 S_038000_TILE_MODE(array_mode) |
1043 unsigned level, pitch, slice, format, offset, array_mode; local in function:r600_init_depth_surface
1054 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1059 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1066 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
2861 unsigned array_mode, lbp local in function:r600_dma_copy_tile
[all...]
H A Devergreen_state.c728 unsigned char array_mode = 0, non_disp_tiling = 0; local in function:evergreen_fill_tex_resource_words
799 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
802 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
805 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
848 S_030004_ARRAY_MODE(array_mode));
1355 unsigned format, array_mode; local in function:evergreen_init_depth_surface
1367 array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1372 array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1386 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
3774 unsigned array_mode, lbp local in function:evergreen_dma_copy_tile
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_texture.c200 enum radeon_surf_mode array_mode,
248 flags, bpe, array_mode, surface);
296 enum radeon_surf_mode *array_mode,
307 *array_mode = RADEON_SURF_MODE_2D;
309 *array_mode = RADEON_SURF_MODE_1D;
311 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1114 enum radeon_surf_mode array_mode; local in function:r600_texture_from_handle
1133 &array_mode, &is_scanout);
1135 r = r600_init_surface(rscreen, &surface, templ, array_mode,
1884 enum radeon_surf_mode array_mode; local in function:r600_texture_from_memobj
197 r600_init_surface(struct r600_common_screen * rscreen,struct radeon_surf * surface,const struct pipe_resource * ptex,enum radeon_surf_mode array_mode,unsigned pitch_in_bytes_override,unsigned offset,bool is_imported,bool is_scanout,bool is_flushed_depth) argument
293 r600_surface_import_metadata(struct r600_common_screen * rscreen,struct radeon_surf * surf,struct radeon_bo_metadata * metadata,enum radeon_surf_mode * array_mode,bool * is_scanout) argument
[all...]
H A Dr600_state.c675 unsigned char swizzle[4], array_mode = 0; local in function:r600_create_sampler_view_custom
744 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
747 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
750 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
756 S_038000_TILE_MODE(array_mode) |
1046 unsigned level, pitch, slice, format, offset, array_mode; local in function:r600_init_depth_surface
1057 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1062 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1069 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
2865 unsigned array_mode, lbp local in function:r600_dma_copy_tile
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state_validate.c26 uint32_t array_size = 0xffff, array_mode = 0; local in function:nv50_validate_fb
52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */
55 assert(mt->layout_3d || !array_mode || array_size == 1);
70 PUSH_DATA (push, array_mode | array_size);
71 nv50->rt_array_mode = array_mode | array_size;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state_validate.c26 uint32_t array_size = 0xffff, array_mode = 0; local in function:nv50_validate_fb
52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */
55 assert(mt->layout_3d || !array_mode || array_size == 1);
70 PUSH_DATA (push, array_mode | array_size);
71 nv50->rt_array_mode = array_mode | array_size;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc.h322 uint32_t array_mode; member in union:ruvd_enc_encode_context_buffer_s::__anon77a2c46b080a
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc.h295 uint32_t array_mode; member in union:ruvd_enc_encode_context_buffer_s::__anonfa6f075e080a

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