Searched refs:bankWidth (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/r800/
H A Degbaddrlib.cpp761 * Additional checks, reduce bankHeight/bankWidth if needed and possible
781 if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize)
785 // Try reducing bankWidth first
786 if (stillGreater && pTileInfo->bankWidth > 1)
788 while (stillGreater && pTileInfo->bankWidth > 0)
790 pTileInfo->bankWidth >>= 1;
792 if (pTileInfo->bankWidth == 0)
794 pTileInfo->bankWidth = 1;
799 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize;
802 // bankWidth i
2970 UINT_32 bankWidth = pTileInfo->bankWidth; local in function:Addr::V1::EgBasedLib::ComputeBankFromCoord
[all...]
H A Dciaddrlib.cpp614 pInfo->bankWidth = 1;
968 tileInfo.banks * tileInfo.bankWidth *
1493 tileInfo.bankWidth * tileInfo.bankHeight;
1504 tileInfo.bankWidth * tileInfo.bankHeight;
1641 pCfg->info.bankWidth = 1;
1734 pCfg->bankWidth = 1 << gbTileMode.f.bank_width;
2184 m_macroTileTable[i].bankWidth * m_macroTileTable[i].bankHeight;
2252 (m_macroTileTable[stencilMacroIndex].bankWidth ==
2253 m_macroTileTable[pOut->macroModeIndex].bankWidth) &&
H A Dsiaddrlib.cpp228 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth);
425 if ((pTileInfo->bankWidth == 1) &&
2523 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
2537 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth;
2648 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
3021 pInfo->bankWidth = 1;
3083 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3529 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight;
3657 key.fields.bankWidth = tileConfig.info.bankWidth;
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/r800/
H A Degbaddrlib.cpp759 * Additional checks, reduce bankHeight/bankWidth if needed and possible
779 if (tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize)
783 // Try reducing bankWidth first
784 if (stillGreater && pTileInfo->bankWidth > 1)
786 while (stillGreater && pTileInfo->bankWidth > 0)
788 pTileInfo->bankWidth >>= 1;
790 if (pTileInfo->bankWidth == 0)
792 pTileInfo->bankWidth = 1;
797 tileSize * pTileInfo->bankWidth * pTileInfo->bankHeight > m_rowSize;
800 // bankWidth i
2971 UINT_32 bankWidth = pTileInfo->bankWidth; local in function:Addr::V1::EgBasedLib::ComputeBankFromCoord
[all...]
H A Dciaddrlib.cpp613 pInfo->bankWidth = 1;
967 tileInfo.banks * tileInfo.bankWidth *
1492 tileInfo.bankWidth * tileInfo.bankHeight;
1503 tileInfo.bankWidth * tileInfo.bankHeight;
1647 pCfg->info.bankWidth = 1;
1751 pCfg->bankWidth = 1 << gbTileMode.f.bank_width;
2200 m_macroTileTable[i].bankWidth * m_macroTileTable[i].bankHeight;
2268 (m_macroTileTable[stencilMacroIndex].bankWidth ==
2269 m_macroTileTable[pOut->macroModeIndex].bankWidth) &&
H A Dsiaddrlib.cpp227 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth);
424 if ((pTileInfo->bankWidth == 1) &&
2523 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
2537 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth;
2648 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
3021 pInfo->bankWidth = 1;
3083 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3529 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight;
3657 key.fields.bankWidth = tileConfig.info.bankWidth;
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/inc/
H A Daddrinterface.h153 UINT_32 bankWidth : 4; ///< Bank width member in struct:_ADDR_EQUATION_KEY::__anona73c1f960208
439 * Valid bankWidth/bankHeight value:
452 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank member in struct:_ADDR_TILEINFO
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.c518 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
783 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/inc/
H A Daddrinterface.h151 UINT_32 bankWidth : 4; ///< Bank width member in struct:_ADDR_EQUATION_KEY::__anond65a1f890208
442 * Valid bankWidth/bankHeight value:
455 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank member in struct:_ADDR_TILEINFO
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c852 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
1114 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;

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