Searched refs:base_level_info (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_image.c347 const struct legacy_surf_level *base_level_info,
364 va += base_level_info->offset;
368 base_level_info->mode == RADEON_SURF_MODE_2D)
379 meta_va += base_level_info->dcc_offset;
421 unsigned pitch = base_level_info->nblk_x * block_width;
1156 const struct legacy_surf_level *base_level_info = NULL; local in function:radv_image_view_make_descriptor
1159 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1161 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1164 base_level_info,
345 si_set_mutable_tex_desc_fields(struct radv_device * device,struct radv_image * image,const struct legacy_surf_level * base_level_info,unsigned plane_id,unsigned base_level,unsigned first_level,unsigned block_width,bool is_stencil,bool is_storage_image,uint32_t * state) argument
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_image.c724 const struct legacy_surf_level *base_level_info, unsigned plane_id,
740 va += (uint64_t)base_level_info->offset_256B * 256;
743 if (chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
827 unsigned pitch = base_level_info->nblk_x * block_width;
1849 const struct legacy_surf_level *base_level_info = NULL; local in function:radv_image_view_make_descriptor
1852 base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->base_mip];
1854 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1860 si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->base_mip,
723 si_set_mutable_tex_desc_fields(struct radv_device * device,struct radv_image * image,const struct legacy_surf_level * base_level_info,unsigned plane_id,unsigned base_level,unsigned first_level,unsigned block_width,bool is_stencil,bool is_storage_image,bool disable_compression,bool enable_write_compression,uint32_t * state) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_descriptors.c306 * \param base_level_info information of the level of BASE_ADDRESS
315 const struct legacy_surf_level *base_level_info,
336 va += base_level_info->offset;
344 * GFX9 doesn't use (legacy) base_level_info.
347 base_level_info->mode == RADEON_SURF_MODE_2D)
359 meta_va += base_level_info->dcc_offset;
360 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
403 unsigned pitch = base_level_info->nblk_x * block_width;
456 sview->base_level_info,
313 si_set_mutable_tex_desc_fields(struct si_screen * sscreen,struct si_texture * tex,const struct legacy_surf_level * base_level_info,unsigned base_level,unsigned first_level,unsigned block_width,bool is_stencil,uint32_t * state) argument
H A Dsi_state.h446 const struct legacy_surf_level *base_level_info,
H A Dsi_pipe.h595 const struct legacy_surf_level *base_level_info; member in struct:si_sampler_view
H A Dsi_state.c4183 view->base_level_info = &surflevel[base_level];
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.h482 const struct legacy_surf_level *base_level_info,
H A Dsi_descriptors.c280 * \param base_level_info information of the level of BASE_ADDRESS
288 const struct legacy_surf_level *base_level_info,
309 va += (uint64_t)base_level_info->offset_256B * 256;
316 * GFX9 doesn't use (legacy) base_level_info.
318 if (sscreen->info.chip_class >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
327 assert(base_level_info->mode == RADEON_SURF_MODE_2D);
413 unsigned pitch = base_level_info->nblk_x * block_width;
469 si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
287 si_set_mutable_tex_desc_fields(struct si_screen * sscreen,struct si_texture * tex,const struct legacy_surf_level * base_level_info,unsigned base_level,unsigned first_level,unsigned block_width,bool is_stencil,uint16_t access,uint32_t * restrict state) argument
H A Dsi_pipe.h678 const struct legacy_surf_level *base_level_info; member in struct:si_sampler_view
H A Dsi_state.c4429 view->base_level_info = &surflevel[base_level];

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