Searched refs:bo_offset (Results 1 - 25 of 40) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.h38 uint64_t bo_offset; member in struct:radv_amdgpu_map_range
H A Dradv_amdgpu_bo.c83 int r = radv_amdgpu_bo_va_op(ws, range->bo ? range->bo->bo : NULL, range->bo_offset, range->size,
105 int r = radv_amdgpu_bo_va_op(ws, range->bo ? range->bo->bo : NULL, range->bo_offset, range->size,
155 uint64_t bo_offset)
207 offset - bo_offset == parent->ranges[first].offset - parent->ranges[first].bo_offset)) {
210 bo_offset = parent->ranges[first].bo_offset;
217 offset - bo_offset == parent->ranges[last].offset - parent->ranges[last].bo_offset)) {
252 new_last.bo_offset
153 radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys * _ws,struct radeon_winsys_bo * _parent,uint64_t offset,uint64_t size,struct radeon_winsys_bo * _bo,uint64_t bo_offset) argument
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_bo.h39 uint64_t bo_offset; member in struct:radv_amdgpu_map_range
H A Dradv_amdgpu_bo.c77 int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset,
93 int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset,
134 struct radeon_winsys_bo *_bo, uint64_t bo_offset)
179 if (parent->ranges[first].bo == bo && (!bo || offset - bo_offset == parent->ranges[first].offset - parent->ranges[first].bo_offset)) {
182 bo_offset = parent->ranges[first].bo_offset;
187 if (parent->ranges[last].bo == bo && (!bo || offset - bo_offset == parent->ranges[last].offset - parent->ranges[last].bo_offset)) {
240 parent->ranges[new_idx].bo_offset
132 radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo * _parent,uint64_t offset,uint64_t size,struct radeon_winsys_bo * _bo,uint64_t bo_offset) argument
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_pack.h35 uint32_t bo_offset; member in struct:fd_reg_pair
62 OUT_RELOC(ring, regs[i].bo, regs[i].bo_offset, regs[i].value, \
H A Dfd6_const.c85 CP_LOAD_STATE6_EXT_SRC_ADDR(.bo = bo, .bo_offset = offset));
92 CP_LOAD_STATE6_EXT_SRC_ADDR(.bo = bo, .bo_offset = offset));
H A Dfd6_gmem.c128 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
163 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
427 .bo_offset =
999 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/
H A Dlima_context.h169 uint32_t bo_offset; member in struct:lima_pp_stream_state
H A Dlima_draw.c549 stream[i] = ps->bo->map + ps->bo_offset + ps->offset[i];
581 i, ps->bo->va + ps->bo_offset + ps->offset[i]);
613 ctx->pp_stream.bo_offset = offset;
637 ctx->pp_stream.bo_offset = 0;
648 ctx->pp_stream.bo_offset = 0;
1628 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
1650 pp_frame.plbu_array_address[i] = ps->bo->va + ps->bo_offset + ps->offset[i];
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
H A Dtu_meta_copy.c237 uint64_t dst_va = dst_image->bo->iova + dst_image->bo_offset + dst_image->layer_size * layer + dst_image->levels[copy_info->imageSubresource.mipLevel].offset;
380 uint64_t src_va = src_buffer->bo->iova + src_buffer->bo_offset + copy_info->bufferOffset + layer_offset * copy_info->bufferImageHeight * src_pitch;
428 uint64_t src_va = src_image->bo->iova + src_image->bo_offset + src_image->layer_size * layer + src_image->levels[copy_info->imageSubresource.mipLevel].offset;
571 uint64_t dst_va = dst_buffer->bo->iova + dst_buffer->bo_offset + copy_info->bufferOffset + layer_offset * copy_info->bufferImageHeight * dst_pitch;
620 uint64_t src_offset = src_buffer->bo_offset + pRegions[i].srcOffset;
621 uint64_t dst_offset = dst_buffer->bo_offset + pRegions[i].dstOffset;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_shader.c388 if (s->bo_offset - offset >= shader->code_size) {
390 shader->bo_offset = offset;
395 offset = align_u64(s->bo_offset + s->code_size, 256);
399 shader->bo_offset = offset;
423 shader->bo_offset = 0;
H A Dradv_radeon_winsys.h260 struct radeon_winsys_bo *bo, uint64_t bo_offset);
H A Dradv_shader.h312 uint64_t bo_offset; member in struct:radv_shader_variant
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_image.c239 uint64_t base_addr = image->bo->iova + image->bo_offset +
241 uint64_t ubwc_addr = image->bo->iova + image->bo_offset +
313 base_addr[i] = image->bo->iova + image->bo_offset +
318 base_addr[i] = image->bo->iova + image->bo_offset +
450 iview->stencil_base_addr = image->bo->iova + image->bo_offset +
H A Dtu_private.h709 VkDeviceSize bo_offset; member in struct:tu_buffer
715 return buffer->bo->iova + buffer->bo_offset;
1100 uint32_t bo_offset; member in struct:tu_reg_value
1413 VkDeviceSize bo_offset; member in struct:tu_image
H A Dtu_cs.h334 uint64_t v = regs[i].bo->iova + regs[i].bo_offset; \
H A Dtu_cmd_buffer.c229 .bo_offset = iview->image->bo_offset + iview->image->lrz_offset),
847 .bo_offset = gb_offset(bcolor_builtin)));
850 .bo_offset = gb_offset(bcolor_builtin)));
884 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = vsc_bo, .bo_offset = size0));
889 .bo_offset = cmd->vsc_prim_strm_pitch * MAX_VSC_PIPES));
1741 cmd->state.index_va = buf->bo->iova + buf->bo_offset + offset;
4262 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4291 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
4325 tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_monitor.c158 uint32_t bo_offset)
162 ice->vtbl.store_register_mem32(batch, GEN9_RPSTAT0, bo, bo_offset, false);
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_allocator.c579 int32_t bo_offset = 0; local in function:anv_block_pool_map
581 if (offset < bo_offset + iter_bo->size) {
585 bo_offset += iter_bo->size;
588 assert(offset >= bo_offset);
589 assert((offset - bo_offset) + size <= bo->size);
591 return bo->map + (offset - bo_offset);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_radeon_winsys.h253 uint64_t bo_offset);
/xsrc/external/mit/MesaLib/dist/src/panfrost/vulkan/
H A Dpanvk_vX_meta_copy.c1167 .buf.ptr = buf->bo->ptr.gpu + buf->bo_offset + region->bufferOffset,
1616 .buf.ptr = buf->bo->ptr.gpu + buf->bo_offset + region->bufferOffset,
1855 .src = src->bo->ptr.gpu + src->bo_offset + region->srcOffset,
1856 .dst = dst->bo->ptr.gpu + dst->bo_offset + region->dstOffset,
2025 .start = dst->bo->ptr.gpu + dst->bo_offset + offset,
2087 .dst = dst->bo->ptr.gpu + dst->bo_offset + offset,
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_performance_query.c943 uint32_t bo_offset)
949 brw_store_register_mem32(brw, bo, GEN7_RPSTAT1, bo_offset);
951 brw_store_register_mem32(brw, bo, GEN9_RPSTAT0, bo_offset);
941 capture_frequency_stat_register(struct brw_context * brw,struct brw_bo * bo,uint32_t bo_offset) argument
H A Dbrw_wm_surface_state.c1668 uint32_t bo_offset; local in function:brw_upload_cs_work_groups_surface
1677 &bo_offset);
1680 bo_offset = brw->compute.num_work_groups_offset;
1684 bo, bo_offset,
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_allocator.c620 uint64_t bo_offset; local in function:anv_block_pool_expand_range
630 bo_offset = pool->start_address + pool->size;
640 bo_offset = 0;
644 bo->offset = bo_offset;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_wm_surface_state.c1680 uint32_t bo_offset; local in function:brw_upload_cs_work_groups_surface
1689 &bo_offset);
1692 bo_offset = brw->compute.num_work_groups_offset;
1696 bo, bo_offset,

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