Searched refs:cb_target_mask (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit; local in function:si_emit_cb_render_state
78 cb_target_mask &= blend->cb_target_mask;
89 cb_target_mask = 0;
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
114 blend->blend_enable_4bit & cb_target_mask &&
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
486 blend->cb_target_mask
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H A Dsi_state.h50 uint32_t cb_target_mask; member in struct:si_state_blend
H A Dsi_pipe.h1643 sctx->queued.named.blend->cb_target_mask;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c77 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask; local in function:si_emit_cb_render_state
88 cb_target_mask = 0;
93 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) {
94 sctx->last_cb_target_mask = cb_target_mask;
104 cb_target_mask);
112 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
150 colormask = (cb_target_mask >> (i * 4)) & 0xf;
486 blend->cb_target_mask = 0;
527 blend->cb_target_mask |
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H A Dsi_state.h55 uint32_t cb_target_mask; member in struct:si_state_blend
H A Dsi_pipe.h1837 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_pipeline.c58 uint32_t cb_target_mask; member in struct:radv_blend_state
706 blend.cb_target_mask = 0;
723 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
838 if (blend.cb_target_mask)
2805 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2809 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
H A Dradv_private.h1406 uint32_t cb_target_mask; member in struct:radv_pipeline::__anone2cea0a71a0a::__anone2cea0a71b08
H A Dradv_cmd_buffer.c767 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_pipe.h324 unsigned cb_target_mask; member in struct:r600_blend_state
H A Dr600_state_common.c202 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
203 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
H A Dr600_state.c362 blend->cb_target_mask = target_mask;
H A Devergreen_state.c349 blend->cb_target_mask = target_mask;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_pipe.h327 unsigned cb_target_mask; member in struct:r600_blend_state
H A Dr600_state_common.c207 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
208 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
H A Dr600_state.c367 blend->cb_target_mask = target_mask;
H A Devergreen_state.c354 blend->cb_target_mask = target_mask;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c54 uint32_t cb_target_mask; member in struct:radv_blend_state
482 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
648 blend.cb_target_mask = 0;
673 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
780 if (blend.cb_target_mask)
5562 pipeline->graphics.cb_target_mask = blend.cb_target_mask;
H A Dradv_cmd_buffer.c1151 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
1359 cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=
1360 pipeline->graphics.cb_target_mask) {
1717 pipeline->graphics.cb_target_mask & d->color_write_enable);
H A Dradv_private.h1819 uint32_t cb_target_mask; member in struct:radv_pipeline::__anon4674665a290a::__anon4674665a2a08

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