Searched refs:coherent (Results 1 - 25 of 46) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/svga/
H A Dsvga_screen_cache.h72 uint32_t coherent:1; member in struct:svga_host_surface_cache_key
H A Dsvga_resource_buffer.c135 !sbuf->key.coherent && !svga->swc->force_coherent) {
324 if (!(svga->swc->force_coherent || sbuf->key.coherent) || sbuf->swbuf) {
369 if (!(svga->swc->force_coherent || sbuf->key.coherent) || sbuf->swbuf)
H A Dsvga_resource_buffer_upload.c195 * coherent memory to avoid implementing memory barriers for
196 * persistent non-coherent memory for now.
198 sbuf->key.coherent = 1;
460 if (swc->force_coherent || sbuf->key.coherent)
661 sbuf->key.coherent) {
885 if (svga->swc->force_coherent || sbuf->key.coherent)
1036 if (svga->swc->force_coherent || sbuf->key.coherent)
H A Dsvga_screen_cache.c573 if (key->coherent)
/xsrc/external/mit/libpciaccess/dist/src/
H A Dcommon_capability.c156 agp_info->coherent = (agp_status & 0x0100) != 0;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dzink_resource.h87 bool coherent; member in struct:zink_resource_object
H A Dzink_resource.c633 obj->coherent = mem_type.propertyFlags & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT;
1294 if (!res->obj->coherent
1296 // Work around for MoltenVk limitation specifically on coherent memory
1419 if (!res->obj->coherent) {
1467 if (!m->obj->coherent) {
H A Dzink_batch.c639 if (!res->obj->coherent && res->obj->persistent_maps)
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D11.0.1.rst82 - nv50,nvc0: flush texture cache in presence of coherent bufs
H A D20.1.5.rst86 - intel/eu: Use non-coherent mode (BTI=253) for stateless A64 messages
H A D20.0.5.rst151 - iris: drop cache coherent cpu mapping for external BO
H A D20.0.8.rst130 - nouveau: allow invalidating coherent/persistent buffer backings
H A D20.1.1.rst115 - nouveau: allow invalidating coherent/persistent buffer backings
H A D21.0.3.rst186 - ac/gpu_info: fix more non-coherent RB and GL2 combinations
/xsrc/external/mit/libpciaccess/dist/include/
H A Dpciaccess.h438 unsigned int coherent:1; member in struct:pci_agp_info
/xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
H A Dir_optimization.h175 bool lower_blend_equation_advanced(gl_linked_shader *shader, bool coherent);
H A Dlower_blend_equation_advanced.cpp464 lower_blend_equation_advanced(struct gl_linked_shader *sh, bool coherent) argument
484 fb->data.memory_coherent = coherent;
H A Dast_type.cpp113 return this->flags.q.coherent
278 input_layout_mask.flags.q.coherent = 1;
880 Q(coherent);
H A Dast.h585 unsigned coherent:1; member in struct:ast_type_qualifier::flags::__anon08d60aa50508
/xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
H A Dir_optimization.h172 bool lower_blend_equation_advanced(gl_linked_shader *shader, bool coherent);
H A Dlower_blend_equation_advanced.cpp466 lower_blend_equation_advanced(struct gl_linked_shader *sh, bool coherent) argument
484 fb->data.memory_coherent = coherent;
H A Dast_type.cpp112 return this->flags.q.coherent
277 input_layout_mask.flags.q.coherent = 1;
877 bad.flags.q.coherent ? " coherent" : "",
H A Dast.h581 unsigned coherent:1; member in struct:ast_type_qualifier::flags::__anona299cf320508
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME-ISA.md132 * DLC ("device level coherent") bit: controls the L1 cache
133 * GLC ("globally coherent") bit: controls the L0 cache
/xsrc/external/mit/MesaLib/dist/docs/drivers/
H A Dvenus.rst206 coherent when the device memory also has

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