Searched refs:cs_prog_data (Results 1 - 25 of 33) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dgen6_constant_state.c293 const struct brw_cs_prog_data *cs_prog_data,
298 (struct brw_stage_prog_data*) cs_prog_data;
306 if (cs_prog_data->push.total.size == 0) {
313 brw_state_batch(brw, ALIGN(cs_prog_data->push.total.size, 64),
319 if (cs_prog_data->push.cross_thread.size > 0) {
322 i < cs_prog_data->push.cross_thread.dwords;
330 if (cs_prog_data->push.per_thread.size > 0) {
331 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
333 8 * (cs_prog_data->push.per_thread.regs * t +
334 cs_prog_data
291 brw_upload_cs_push_constants(struct brw_context * brw,const struct gl_program * prog,const struct brw_cs_prog_data * cs_prog_data,struct brw_stage_state * stage_state) argument
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H A Dbrw_state.h280 const struct brw_cs_prog_data *cs_prog_data,
H A DgenX_state_upload.c4278 struct brw_cs_prog_data *cs_prog_data = local in function:genX
4282 brw_upload_cs_push_constants(brw, cp, cs_prog_data, stage_state);
4343 struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data); local in function:genX
4436 ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
4437 cs_prog_data->push.cross_thread.regs, 2);
4441 if (cs_prog_data->push.total.size > 0) {
4444 ALIGN(cs_prog_data->push.total.size, 64);
4457 .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
4458 .NumberofThreadsinGPGPUThreadGroup = cs_prog_data
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H A Dbrw_wm_surface_state.c1660 const struct brw_cs_prog_data *cs_prog_data = local in function:brw_upload_cs_work_groups_surface
1663 if (prog && cs_prog_data->uses_num_work_groups) {
1665 cs_prog_data->binding_table.work_groups_start;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dgfx6_constant_state.c298 const struct brw_cs_prog_data *cs_prog_data,
303 (struct brw_stage_prog_data*) cs_prog_data;
312 brw_cs_get_dispatch_info(&brw->screen->devinfo, cs_prog_data,
315 brw_cs_push_const_total_size(cs_prog_data, dispatch.threads);
330 if (cs_prog_data->push.cross_thread.size > 0) {
333 i < cs_prog_data->push.cross_thread.dwords;
341 if (cs_prog_data->push.per_thread.size > 0) {
344 8 * (cs_prog_data->push.per_thread.regs * t +
345 cs_prog_data->push.cross_thread.regs);
346 unsigned src = cs_prog_data
296 brw_upload_cs_push_constants(struct brw_context * brw,const struct gl_program * prog,const struct brw_cs_prog_data * cs_prog_data,struct brw_stage_state * stage_state) argument
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H A Dbrw_state.h277 const struct brw_cs_prog_data *cs_prog_data,
H A DgenX_state_upload.c4205 struct brw_cs_prog_data *cs_prog_data = local in function:genX
4209 brw_upload_cs_push_constants(brw, cp, cs_prog_data, stage_state);
4270 struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data); local in function:genX
4274 brw_cs_get_dispatch_info(devinfo, cs_prog_data, brw->compute.group_size);
4359 ALIGN(cs_prog_data->push.per_thread.regs * dispatch.threads +
4360 cs_prog_data->push.cross_thread.regs, 2);
4365 brw_cs_push_const_total_size(cs_prog_data, dispatch.threads);
4377 brw_cs_prog_data_prog_offset(cs_prog_data,
4386 .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
4390 .BarrierEnable = cs_prog_data
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H A Dbrw_wm_surface_state.c1672 const struct brw_cs_prog_data *cs_prog_data = local in function:brw_upload_cs_work_groups_surface
1675 if (prog && cs_prog_data->uses_num_work_groups) {
1677 cs_prog_data->binding_table.work_groups_start;
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp.c296 struct brw_cs_prog_data *cs_prog_data)
303 memset(cs_prog_data, 0, sizeof(*cs_prog_data));
309 cs_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
321 cs_prog_data->base.nr_params = nr_params;
322 cs_prog_data->base.param = rzalloc_array(NULL, uint32_t, nr_params);
329 .prog_data = cs_prog_data,
336 ralloc_free(cs_prog_data->base.param);
337 cs_prog_data->base.param = NULL;
293 blorp_compile_cs(struct blorp_context * blorp,void * mem_ctx,struct nir_shader * nir,struct brw_cs_prog_key * cs_key,struct brw_cs_prog_data * cs_prog_data) argument
H A Dblorp_genX_exec.h2020 const struct brw_cs_prog_data *cs_prog_data = params->cs_prog_data; local in function:blorp_get_compute_push_const
2022 ALIGN(brw_cs_push_const_total_size(cs_prog_data, threads), 64);
2023 assert(cs_prog_data->push.cross_thread.size +
2024 cs_prog_data->push.per_thread.size == sizeof(params->wm_inputs));
2044 if (cs_prog_data->push.cross_thread.size > 0) {
2045 memcpy(dst, src, cs_prog_data->push.cross_thread.size);
2046 dst += cs_prog_data->push.cross_thread.size;
2047 src += cs_prog_data->push.cross_thread.size;
2050 assert(GFX_VERx10 < 125 || cs_prog_data
2078 const struct brw_cs_prog_data *cs_prog_data = params->cs_prog_data; local in function:blorp_exec_compute
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H A Dblorp_priv.h236 struct brw_cs_prog_data *cs_prog_data; member in struct:blorp_params
454 struct brw_cs_prog_data *cs_prog_data);
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_cmd_buffer.c781 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline); local in function:anv_cmd_buffer_cs_push_constants
782 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
785 if (cs_prog_data->push.total.size == 0)
791 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
800 if (cs_prog_data->push.cross_thread.size > 0) {
802 i < cs_prog_data->push.cross_thread.dwords;
810 if (cs_prog_data->push.per_thread.size > 0) {
811 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
813 8 * (cs_prog_data->push.per_thread.regs * t +
814 cs_prog_data
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H A DgenX_pipeline.c2050 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline); local in function:compute_pipeline_create
2052 anv_pipeline_setup_l3_config(pipeline, cs_prog_data->base.total_shared > 0);
2054 uint32_t group_size = cs_prog_data->local_size[0] *
2055 cs_prog_data->local_size[1] * cs_prog_data->local_size[2];
2056 uint32_t remainder = group_size & (cs_prog_data->simd_size - 1);
2061 pipeline->cs_right_mask = ~0u >> (32 - cs_prog_data->simd_size);
2064 ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
2065 cs_prog_data
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/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_cmd_buffer.c1174 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline); local in function:anv_cmd_buffer_cs_push_constants
1178 brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
1180 brw_cs_push_const_total_size(cs_prog_data, dispatch.threads);
1202 if (cs_prog_data->push.cross_thread.size > 0) {
1203 memcpy(dst, src, cs_prog_data->push.cross_thread.size);
1204 dst += cs_prog_data->push.cross_thread.size;
1205 src += cs_prog_data->push.cross_thread.size;
1208 if (cs_prog_data->push.per_thread.size > 0) {
1210 memcpy(dst, src, cs_prog_data->push.per_thread.size);
1214 (range->start * 32 + cs_prog_data
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H A DgenX_pipeline.c2619 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline); local in function:emit_compute_state
2620 anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
2640 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline); local in function:emit_compute_state
2642 anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
2645 brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
2647 ALIGN(cs_prog_data->push.per_thread.regs * dispatch.threads +
2648 cs_prog_data->push.cross_thread.regs, 2);
2698 brw_cs_prog_data_prog_offset(cs_prog_data, dispatch.simd_size),
2706 .BarrierEnable = cs_prog_data->uses_barrier,
2708 encode_slm_size(GFX_VER, cs_prog_data
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_program.c1316 struct brw_cs_prog_data *cs_prog_data = local in function:iris_compile_cs
1318 struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
1325 cs_prog_data->binding_table.work_groups_start = 0;
1337 brw_compile_cs(compiler, &ice->dbg, mem_ctx, key, cs_prog_data,
1387 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, argument
1390 assert(cs_prog_data->push.total.size > 0);
1391 assert(cs_prog_data->push.cross_thread.size == 0);
1392 assert(cs_prog_data->push.per_thread.dwords == 1);
1393 assert(cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
1394 for (unsigned t = 0; t < cs_prog_data
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H A Diris_state.c3829 struct brw_cs_prog_data *cs_prog_data = (void *) shader->prog_data; local in function:iris_store_cs_state
3834 desc.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs;
3835 desc.NumberofThreadsinGPGPUThreadGroup = cs_prog_data->threads;
3838 desc.BarrierEnable = cs_prog_data->uses_barrier;
3840 cs_prog_data->push.cross_thread.regs;
5433 struct brw_cs_prog_data *cs_prog_data = (void *) prog_data; local in function:iris_upload_compute_state
5490 ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
5491 cs_prog_data->push.cross_thread.regs, 2);
5497 assert(cs_prog_data
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H A Diris_context.h672 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_state.c4569 struct brw_cs_prog_data *cs_prog_data = (void *) shader->prog_data; local in function:iris_store_cs_state
4574 desc.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs;
4576 cs_prog_data->push.cross_thread.regs;
4578 assert(cs_prog_data->push.per_thread.regs == 0);
4579 assert(cs_prog_data->push.cross_thread.regs == 0);
4581 desc.BarrierEnable = cs_prog_data->uses_barrier;
6917 struct brw_cs_prog_data *cs_prog_data = (void *) prog_data; local in function:iris_upload_compute_walker
6919 brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
6951 .NumberOfBarriers = cs_prog_data->uses_barrier,
6956 assert(brw_cs_push_const_total_size(cs_prog_data, dispatc
6978 struct brw_cs_prog_data *cs_prog_data = (void *) prog_data; local in function:iris_upload_gpgpu_walker
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H A Diris_program.c2231 struct brw_cs_prog_data *cs_prog_data = local in function:iris_compile_cs
2233 struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
2257 .prog_data = cs_prog_data,
2334 iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, argument
2338 assert(brw_cs_push_const_total_size(cs_prog_data, threads) > 0);
2339 assert(cs_prog_data->push.cross_thread.size == 0);
2340 assert(cs_prog_data->push.per_thread.dwords == 1);
2341 assert(cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
H A Diris_context.h867 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_fs.cpp8147 struct brw_cs_prog_data *cs_prog_data)
8149 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
8172 fill_push_const_block_info(&cs_prog_data->push.cross_thread, cross_thread_dwords);
8173 fill_push_const_block_info(&cs_prog_data->push.per_thread, per_thread_dwords);
8176 (cs_prog_data->push.per_thread.size * cs_prog_data->threads +
8177 cs_prog_data->push.cross_thread.size) / 4;
8178 fill_push_const_block_info(&cs_prog_data->push.total, total_dwords);
8180 assert(cs_prog_data->push.cross_thread.dwords % 8 == 0 ||
8181 cs_prog_data
8146 cs_fill_push_const_info(const struct gen_device_info * devinfo,struct brw_cs_prog_data * cs_prog_data) argument
8188 cs_set_simd_size(struct brw_cs_prog_data * cs_prog_data,unsigned size) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_program.c2519 struct brw_cs_prog_data *cs_prog_data = local in function:crocus_compile_cs
2521 struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
2541 .prog_data = cs_prog_data,
2562 prog_data, sizeof(*cs_prog_data), NULL,
2619 crocus_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, argument
2623 assert(brw_cs_push_const_total_size(cs_prog_data, threads) > 0);
2624 assert(cs_prog_data->push.cross_thread.size == 0);
2625 assert(cs_prog_data->push.per_thread.dwords == 1);
2626 assert(cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
H A Dcrocus_context.h775 void crocus_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_fs.cpp9971 brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data, argument
9974 assert(cs_prog_data->push.per_thread.size % REG_SIZE == 0);
9975 assert(cs_prog_data->push.cross_thread.size % REG_SIZE == 0);
9976 return cs_prog_data->push.per_thread.size * threads +
9977 cs_prog_data->push.cross_thread.size;
9990 struct brw_cs_prog_data *cs_prog_data)
9992 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
10015 fill_push_const_block_info(&cs_prog_data->push.cross_thread, cross_thread_dwords);
10016 fill_push_const_block_info(&cs_prog_data->push.per_thread, per_thread_dwords);
10018 assert(cs_prog_data
9989 cs_fill_push_const_info(const struct intel_device_info * devinfo,struct brw_cs_prog_data * cs_prog_data) argument
10346 brw_cs_simd_size_for_group_size(const struct intel_device_info * devinfo,const struct brw_cs_prog_data * cs_prog_data,unsigned group_size) argument
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