Searched refs:dpll (Results 1 - 2 of 2) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_display.c1520 uint32_t dpll = 0, fp = 0, dspcntr, pipeconf, lvds_bits = 0; local in function:i830_crtc_mode_set
1619 dpll = DPLL_VGA_MODE_DIS;
1622 dpll |= DPLLB_MODE_LVDS;
1624 dpll |= DPLLB_MODE_DAC_SERIAL;
1627 dpll |= DPLL_DVO_HIGH_SPEED;
1631 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1637 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1639 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1645 dpll |
2200 uint32_t dpll = INREG((pipe == 0) ? DPLL_A : DPLL_B); local in function:i830_crtc_clock_get
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H A Di830_debug.c1548 int fp, dpll; local in function:i830DumpRegs
1597 dpll = INREG(pipe == 0 ? DPLL_A : DPLL_B);
1611 switch ((dpll >> 24) & 0x3) {
1625 i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT_IGD) & 0x1ff;
1627 i = (dpll >> DPLL_FPA01_P1_POST_DIV_SHIFT) & 0xff;
1656 switch ((dpll >> 13) & 0x3) {
1680 switch ((dpll >> 16) & 0x3f) {
1690 (dpll >> 16) & 0x3f);
1696 if (dpll & (1 << 23))
1700 if (dpll
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