Searched refs:dst_sel (Results 1 - 25 of 32) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/sb/
H A Dsb_bc_builder.cpp545 .DST_SEL_X(bc.dst_sel[0])
546 .DST_SEL_Y(bc.dst_sel[1])
547 .DST_SEL_Z(bc.dst_sel[2])
548 .DST_SEL_W(bc.dst_sel[3])
596 .DST_SEL_X(bc.dst_sel[0])
597 .DST_SEL_Y(bc.dst_sel[1])
598 .DST_SEL_Z(bc.dst_sel[2])
599 .DST_SEL_W(bc.dst_sel[3]);
639 .DST_SEL_X(bc.dst_sel[0])
640 .DST_SEL_Y(bc.dst_sel[
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H A Dsb_bc_decoder.cpp480 bc.dst_sel[0] = w1.get_DST_SEL_X();
481 bc.dst_sel[1] = w1.get_DST_SEL_Y();
482 bc.dst_sel[2] = w1.get_DST_SEL_Z();
483 bc.dst_sel[3] = w1.get_DST_SEL_W();
529 bc.dst_sel[0] = w2.get_DST_SEL_X();
530 bc.dst_sel[1] = w2.get_DST_SEL_Y();
531 bc.dst_sel[2] = w2.get_DST_SEL_Z();
532 bc.dst_sel[3] = w2.get_DST_SEL_W();
561 bc.dst_sel[0] = w1.get_DST_SEL_X();
562 bc.dst_sel[
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H A Dsb_bc_finalize.cpp494 dst.bc.dst_sel[chan] = SEL_MASK;
660 unsigned sel = f->bc.dst_sel[chan];
694 f->bc.dst_sel[i] = dst_swz[i];
697 f->bc.dst_sel[0] = SEL_MASK;
H A Dsb_bc.h550 unsigned dst_sel[4]; member in struct:r600_sb::bc_fetch
H A Dsb_bc_dump.cpp491 s << chans[n.bc.dst_sel[k]];
H A Dsb_expr.cpp310 if (n.bc.dst_sel[chan] == SEL_0)
312 else if (n.bc.dst_sel[chan] == SEL_1)
H A Dsb_bc_parser.cpp708 if (n->bc.dst_sel[s] != SEL_MASK)
711 // are using, but original n->bc.dst_sel should be taken into
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sb/
H A Dsb_bc_builder.cpp545 .DST_SEL_X(bc.dst_sel[0])
546 .DST_SEL_Y(bc.dst_sel[1])
547 .DST_SEL_Z(bc.dst_sel[2])
548 .DST_SEL_W(bc.dst_sel[3])
596 .DST_SEL_X(bc.dst_sel[0])
597 .DST_SEL_Y(bc.dst_sel[1])
598 .DST_SEL_Z(bc.dst_sel[2])
599 .DST_SEL_W(bc.dst_sel[3]);
639 .DST_SEL_X(bc.dst_sel[0])
640 .DST_SEL_Y(bc.dst_sel[
[all...]
H A Dsb_bc_decoder.cpp480 bc.dst_sel[0] = w1.get_DST_SEL_X();
481 bc.dst_sel[1] = w1.get_DST_SEL_Y();
482 bc.dst_sel[2] = w1.get_DST_SEL_Z();
483 bc.dst_sel[3] = w1.get_DST_SEL_W();
529 bc.dst_sel[0] = w2.get_DST_SEL_X();
530 bc.dst_sel[1] = w2.get_DST_SEL_Y();
531 bc.dst_sel[2] = w2.get_DST_SEL_Z();
532 bc.dst_sel[3] = w2.get_DST_SEL_W();
562 bc.dst_sel[0] = w1.get_DST_SEL_X();
563 bc.dst_sel[
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H A Dsb_bc_finalize.cpp494 dst.bc.dst_sel[chan] = SEL_MASK;
660 unsigned sel = f->bc.dst_sel[chan];
694 f->bc.dst_sel[i] = dst_swz[i];
697 f->bc.dst_sel[0] = SEL_MASK;
H A Dsb_bc.h584 unsigned dst_sel[4]; member in struct:r600_sb::bc_fetch
H A Dsb_bc_dump.cpp493 s << chans[n.bc.dst_sel[k]];
H A Dsb_expr.cpp310 if (n.bc.dst_sel[chan] == SEL_0)
312 else if (n.bc.dst_sel[chan] == SEL_1)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c586 unsigned offset, unsigned size, unsigned dst_sel,
594 if (sctx->chip_class == SI && dst_sel == V_370_MEM)
595 dst_sel = V_370_MEM_GRBM;
602 radeon_emit(cs, S_370_DST_SEL(dst_sel) |
611 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
630 COPY_DATA_DST_SEL(dst_sel) |
585 si_cp_write_data(struct si_context * sctx,struct si_resource * buf,unsigned offset,unsigned size,unsigned dst_sel,unsigned engine,const void * data) argument
610 si_cp_copy_data(struct si_context * sctx,unsigned dst_sel,struct si_resource * dst,unsigned dst_offset,unsigned src_sel,struct si_resource * src,unsigned src_offset) argument
H A Dsi_fence.c61 * \param dst_sel MEM or TC_L2
71 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
80 unsigned sel = EOP_DST_SEL(dst_sel) |
69 si_cp_release_mem(struct si_context * ctx,unsigned event,unsigned event_flags,unsigned dst_sel,unsigned int_sel,unsigned data_sel,struct si_resource * buf,uint64_t va,uint32_t new_fence,unsigned query_type) argument
H A Dsi_pipe.h1244 unsigned offset, unsigned size, unsigned dst_sel,
1247 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1282 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c480 unsigned size, unsigned dst_sel, unsigned engine, const void *data)
487 if (sctx->chip_class == GFX6 && dst_sel == V_370_MEM)
488 dst_sel = V_370_MEM_GRBM;
495 radeon_emit(S_370_DST_SEL(dst_sel) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine));
502 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel, argument
519 radeon_emit(COPY_DATA_SRC_SEL(src_sel) | COPY_DATA_DST_SEL(dst_sel) | COPY_DATA_WR_CONFIRM);
479 si_cp_write_data(struct si_context * sctx,struct si_resource * buf,unsigned offset,unsigned size,unsigned dst_sel,unsigned engine,const void * data) argument
H A Dsi_fence.c59 * \param dst_sel MEM or TC_L2
68 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
75 unsigned sel = EOP_DST_SEL(dst_sel) | EOP_INT_SEL(int_sel) | EOP_DATA_SEL(data_sel);
67 si_cp_release_mem(struct si_context * ctx,struct radeon_cmdbuf * cs,unsigned event,unsigned event_flags,unsigned dst_sel,unsigned int_sel,unsigned data_sel,struct si_resource * buf,uint64_t va,uint32_t new_fence,unsigned query_type) argument
H A Dsi_pipe.h1398 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1399 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1423 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_validate.cpp170 check(def.bytes() >= sdwa.dst_sel.size() + sdwa.dst_sel.offset(),
173 sdwa.dst_sel.size() == 1 || sdwa.dst_sel.size() == 2 || sdwa.dst_sel.size() == 4,
175 check(sdwa.dst_sel.offset() % sdwa.dst_sel.size() == 0, "Invalid selection offset",
177 check(def.bytes() == 4 || def.bytes() == sdwa.dst_sel.size(),
178 "SDWA dst_sel size must be definition size for subdword definitions",
180 check(def.bytes() == 4 || sdwa.dst_sel
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H A Daco_opt_value_numbering.cpp188 aSDWA.dst_sel == bSDWA.dst_sel && aSDWA.abs[0] == bSDWA.abs[0] &&
H A Daco_print_ir.cpp615 char sext = sdwa.dst_sel.sign_extend() ? 's' : 'u';
616 unsigned offset = sdwa.dst_sel.offset();
619 switch (sdwa.dst_sel.size()) {
620 case 1: fprintf(output, " dst_sel:%cbyte%u", sext, offset); break;
621 case 2: fprintf(output, " dst_sel:%cword%u", sext, offset >> 1); break;
622 case 4: fprintf(output, " dst_sel:dword"); break;
H A Daco_assembler.cpp709 encoding |= sdwa.dst_sel.to_sdwa_sel(instr->definitions[0].physReg().byte()) << 8;
710 uint32_t dst_u = sdwa.dst_sel.sign_extend() ? 1 : 0;
H A Daco_ir.cpp282 sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c839 unsigned event, unsigned event_flags, unsigned dst_sel,
847 unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel);
882 assert(event_flags == 0 && dst_sel == EOP_DST_SEL_MEM &&
838 si_cs_emit_write_event_eop(struct radeon_cmdbuf * cs,enum chip_class chip_class,bool is_mec,unsigned event,unsigned event_flags,unsigned dst_sel,unsigned data_sel,uint64_t va,uint32_t new_fence,uint64_t gfx9_eop_bug_va) argument

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