Searched refs:flushes (Results 1 - 25 of 34) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.0.2.rst51 - radv: Emit pending flushes before executing a secondary command
59 - radv: Emit cache flushes before CP DMA.
60 - Revert "radv: Emit cache flushes before CP DMA."
H A D18.1.7.rst54 - r600/eg: rework atomic counter emission with flushes
H A D10.0.3.rst95 - i965/gen6/blorp: Emit more flushes to workaround hangs
H A D20.0.1.rst154 - iris: Apply the flushes when switching pipelines.
H A D20.2.3.rst136 - iris: Flush dmabufs during context flushes
H A D8.0.1.rst120 - i965: Emit Ivybridge VS workaround flushes.
H A D13.0.6.rst57 - radv: Emit pending flushes before executing a secondary command
75 - radv: Emit cache flushes before CP DMA.
H A D10.3.3.rst136 - freedreno: "fix" problems with excessive flushes
H A D17.1.4.rst122 - i965: Do an end-of-pipe sync after flushes
H A D20.2.5.rst55 - radv: Fix a hang on CB change by adding flushes.
H A D17.3.4.rst212 - radv: remove predication on cache flushes
H A D7.11.1.rst260 - i965: Emit depth stalls and flushes before changing depth state on
H A D21.3.0.rst232 - panfrost: Log reasons for flushes
538 - radv: Add RT cache flushes.
1675 - iris: Add separate dirty bit for VBO flushes.
1681 - iris: Use separate dirty bits for UBO and SSBO flushes.
1960 - intel/eu: Set scope to TILE for TGM flushes
2851 - zink: if descriptor updating flushes, re-call draw/compute
3790 - radv: fix missing cache flushes when clearing HTILE levels on GFX10+
H A D21.2.0.rst140 - freedreno: tex-miplevel-selection causes a creation of too many BOs without flushes, causing a crash
311 - v3d/simulator: wait for cache flushes
906 - panfrost: Eliminate redundant flushes with AFBC
2414 - iris: reduce redundant tile cache flushes
2424 - anv: remove unnecessary Tile Cache flushes
3512 - glthread: change when glFlush flushes asynchronously
3922 - zink: reapply resource/surface refs after app flushes
4516 - freedreno: last_fence optimization for TC async flushes
4603 - freedreno: Fix flushes with NULL batch
4848 - radv: fix missing cache flushes whe
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H A D19.1.0.rst3036 - iris: do PIPELINE_SELECT for render engine, add flushes, GLK hacks
3256 - iris: Add missing depth cache flushes
3305 - iris: Move depth/stencil flushes so they actually do something
3322 - iris: Skip resolves and flushes altogether if unnecessary
3353 - iris: Mark constants dirty on transfer unmap even if no flushes occur
H A D20.2.0.rst463 - panfrost: Add debug print before query flushes
1151 - tu: Remove useless post-binning flushes
2187 - iris: Perform compute predraw flushes from compute batch.
2738 - turnip: add emit renderpass cache flushes for sysmem 3D CmdClearAttachments
H A D20.3.0.rst865 - radv: Include flushes in the barrier.
866 - radv: Record cache flushes for RGP.
885 - radv: Fix a hang on CB change by adding flushes.
3883 - iris: Flush dmabufs during context flushes
/xsrc/external/mit/libX11/dist/src/
H A DInitExt.c443 for (ext = dpy->flushes; ext && ext != e; ext = ext->next)
446 e->next_flush = dpy->flushes;
447 dpy->flushes = e;
H A DOpenDis.c188 dpy->flushes = NULL;
H A Dxcb_io.c579 for(ext = dpy->flushes; ext; ext = ext->next_flush)
/xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c70 enum tu_cmd_flush_bits flushes)
73 flushes |= TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_ALL_INVALIDATE;
76 flushes |= TU_CMD_FLAG_WAIT_MEM_WRITES |
85 if (flushes & (TU_CMD_FLAG_CCU_FLUSH_COLOR |
88 if (flushes & (TU_CMD_FLAG_CCU_FLUSH_DEPTH |
91 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_COLOR)
93 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_DEPTH)
95 if (flushes & TU_CMD_FLAG_CACHE_FLUSH)
97 if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
99 if (flushes
68 tu6_emit_flushes(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,enum tu_cmd_flush_bits flushes) argument
142 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits; local in function:tu_emit_cache_flush_ccu
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/xsrc/external/mit/MesaLib/dist/docs/gallium/
H A Dbuffermapping.rst191 flushes).
273 just changes which region it flushes. The same GL buffer name is used in every
H A Dcontext.rst742 This function flushes all pending writes to the currently-set surfaces and
753 This function flushes caches according to which of the PIPE_BARRIER_* flags
/xsrc/external/mit/libX11/dist/include/X11/
H A DXlibint.h177 struct _XExten *flushes; /* Flush hooks */ member in struct:_XDisplay
926 struct _XExten *next_flush; /* next in list of those with flushes */
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/
H A Dcontext.rst714 This function flushes all pending writes to the currently-set surfaces and
725 This function flushes caches according to which of the PIPE_BARRIER_* flags

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