Searched refs:fmask_offset (Results 1 - 16 of 16) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_surface.c448 surf_ws->fmask_offset = align64(surf_ws->total_size, 1 << surf_ws->fmask_alignment_log2);
449 surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size;
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.h379 uint64_t fmask_offset; member in struct:radeon_surf
H A Dac_surface.c2403 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0;
2407 surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2);
2408 surf->total_size = surf->fmask_offset + surf->fmask_size;
2452 if (!surf->fmask_offset && !surf->cmask_offset) {
2834 if (surf->fmask_offset)
2835 surf->fmask_offset += offset;
2930 if (surf->fmask_offset)
2934 surf->fmask_offset, surf->fmask_size,
2980 if (surf->fmask_offset)
2985 surf->fmask_offset, sur
[all...]
H A Dac_surface_modifier_test.c259 assert(surf.fmask_offset == 0);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state.c2458 if (tex->surface.fmask_offset) {
2695 if (tex->surface.fmask_offset) {
2894 if (tex->surface.fmask_offset)
3100 if (tex->surface.fmask_offset) {
3101 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3127 if (!tex->surface.fmask_offset)
3174 if (!tex->surface.fmask_offset)
3214 if (!tex->surface.fmask_offset)
3229 if (tex->surface.fmask_offset) {
3901 if (tex->surface.fmask_offset) {
[all...]
H A Dsi_compute_blit.c762 si_clear_buffer(sctx, tex, stex->surface.fmask_offset, stex->surface.fmask_size,
H A Dsi_texture.c472 tex->surface.fmask_offset = new_tex->surface.fmask_offset;
H A Dsi_blit.c532 if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) {
H A Dsi_descriptors.c755 assert(fmask_desc || tex->surface.fmask_offset == 0);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c560 tex->fmask_offset = new_tex->fmask_offset;
1077 tex->fmask_offset,
1132 tex->fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
1276 tex->fmask_offset = align64(tex->size,
1278 tex->size = tex->fmask_offset + tex->surface.fmask_size;
H A Dsi_pipe.h288 uint64_t fmask_offset; member in struct:si_texture
H A Dsi_state.c3083 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3902 va = tex->buffer.gpu_address + tex->fmask_offset;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_image.c981 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
1135 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
H A Dradv_meta_clear.c1445 uint64_t offset = image->offset + image->planes[0].surface.fmask_offset;
H A Dradv_private.h2028 return image->planes[0].surface.fmask_offset;
H A Dradv_device.c6701 va = radv_buffer_get_va(iview->image->bo) + iview->image->offset + surf->fmask_offset;

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