| /xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/ |
| H A D | v3dv_meta_clear.c | 470 struct nir_shader *fs_nir,
499 if (fs_nir) {
500 v3dv_shader_module_internal_init(device, &fs_m, fs_nir);
584 ralloc_free(fs_nir);
602 nir_shader *fs_nir = get_color_clear_rect_fs(rt_idx, format); local in function:create_color_clear_pipeline
641 vs_nir, gs_nir, fs_nir,
664 nir_shader *fs_nir = has_depth ? get_depth_clear_rect_fs() : NULL; local in function:create_depth_clear_pipeline
700 vs_nir, gs_nir, fs_nir,
464 create_pipeline(struct v3dv_device * device,struct v3dv_render_pass * pass,uint32_t subpass_idx,uint32_t samples,struct nir_shader * vs_nir,struct nir_shader * gs_nir,struct nir_shader * fs_nir,const VkPipelineVertexInputStateCreateInfo * vi_state,const VkPipelineDepthStencilStateCreateInfo * ds_state,const VkPipelineColorBlendStateCreateInfo * cb_state,const VkPipelineLayout layout,VkPipeline * pipeline) argument
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| H A D | v3dv_meta_copy.c | 1579 struct nir_shader *fs_nir,
1814 nir_shader *fs_nir = get_texel_buffer_copy_fs(device, format, cswizzle); local in function:create_texel_buffer_copy_pipeline
1851 vs_nir, gs_nir, fs_nir,
3343 struct nir_shader *fs_nir,
3358 v3dv_shader_module_internal_init(device, &fs_m, fs_nir);
3455 ralloc_free(fs_nir);
3503 nir_shader *fs_nir = local in function:create_blit_pipeline
3541 vs_nir, NULL, fs_nir,
3339 create_pipeline(struct v3dv_device * device,struct v3dv_render_pass * pass,struct nir_shader * vs_nir,struct nir_shader * gs_nir,struct nir_shader * fs_nir,const VkPipelineVertexInputStateCreateInfo * vi_state,const VkPipelineDepthStencilStateCreateInfo * ds_state,const VkPipelineColorBlendStateCreateInfo * cb_state,const VkPipelineMultisampleStateCreateInfo * ms_state,const VkPipelineLayout layout,VkPipeline * pipeline) argument
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| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| H A D | radv_meta_clear.c | 78 struct nir_shader *vs_nir, struct nir_shader *fs_nir,
92 .stageCount = fs_nir ? 2 : 1,
104 .module = vk_shader_module_handle_from_nir(fs_nir),
171 ralloc_free(fs_nir);
253 struct nir_shader *fs_nir; local in function:create_color_pipeline
262 build_color_shaders(&vs_nir, &fs_nir, frag_output);
295 create_pipeline(device, radv_render_pass_from_handle(pass), samples, vs_nir, fs_nir,
587 struct nir_shader *vs_nir, *fs_nir; local in function:create_depthstencil_pipeline
596 build_depthstencil_shader(&vs_nir, &fs_nir, unrestricted);
639 create_pipeline(device, radv_render_pass_from_handle(render_pass), samples, vs_nir, fs_nir,
77 create_pipeline(struct radv_device * device,struct radv_render_pass * render_pass,uint32_t samples,struct nir_shader * vs_nir,struct nir_shader * fs_nir,const VkPipelineVertexInputStateCreateInfo * vi_state,const VkPipelineDepthStencilStateCreateInfo * ds_state,const VkPipelineColorBlendStateCreateInfo * cb_state,const VkPipelineLayout layout,const struct radv_graphics_pipeline_create_info * extra,const VkAllocationCallbacks * alloc,VkPipeline * pipeline) argument
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| H A D | radv_meta_clear.c | 99 struct nir_shader *fs_nir,
112 struct radv_shader_module fs_m = { .nir = fs_nir };
118 .stageCount = fs_nir ? 2 : 1,
192 ralloc_free(fs_nir);
252 struct nir_shader *fs_nir; local in function:create_color_pipeline
261 build_color_shaders(&vs_nir, &fs_nir, frag_output);
298 samples, vs_nir, fs_nir, &vi_state, &ds_state, &cb_state,
567 struct nir_shader *vs_nir, *fs_nir; local in function:create_depthstencil_pipeline
576 build_depthstencil_shader(&vs_nir, &fs_nir);
620 samples, vs_nir, fs_nir,
95 create_pipeline(struct radv_device * device,struct radv_render_pass * render_pass,uint32_t samples,struct nir_shader * vs_nir,struct nir_shader * fs_nir,const VkPipelineVertexInputStateCreateInfo * vi_state,const VkPipelineDepthStencilStateCreateInfo * ds_state,const VkPipelineColorBlendStateCreateInfo * cb_state,const VkPipelineLayout layout,const struct radv_graphics_pipeline_create_info * extra,const VkAllocationCallbacks * alloc,VkPipeline * pipeline) argument
[all...] |