Searched refs:gbTileMode (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp1586 GB_TILE_MODE gbTileMode; local in function:Addr::V1::CiLib::ReadGbTileMode
1587 gbTileMode.val = regValue;
1589 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode_new);
1592 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.alt_pipe_config + 1);
1596 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
1601 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
1605 pCfg->info.tileSplitBytes = 1 << gbTileMode.f.sample_split;
1608 UINT_32 regArrayMode = gbTileMode.f.array_mode;
1736 GB_MACROTILE_MODE gbTileMode; local in function:Addr::V1::CiLib::ReadGbMacroTileCfg
1737 gbTileMode
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H A Dsiaddrlib.cpp3078 GB_TILE_MODE gbTileMode; local in function:Addr::V1::SiLib::ReadGbTileMode
3079 gbTileMode.val = regValue;
3081 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
3082 pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
3083 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3084 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
3085 pCfg->info.macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
3086 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
3087 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
3089 UINT_32 regArrayMode = gbTileMode
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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/r800/
H A Dciaddrlib.cpp1587 GB_TILE_MODE gbTileMode; local in function:Addr::V1::CiLib::ReadGbTileMode
1588 gbTileMode.val = regValue;
1590 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode_new);
1591 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
1595 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
1599 pCfg->info.tileSplitBytes = 1 << gbTileMode.f.sample_split;
1602 UINT_32 regArrayMode = gbTileMode.f.array_mode;
1730 GB_MACROTILE_MODE gbTileMode; local in function:Addr::V1::CiLib::ReadGbMacroTileCfg
1731 gbTileMode.val = regValue;
1733 pCfg->bankHeight = 1 << gbTileMode
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H A Dsiaddrlib.cpp3078 GB_TILE_MODE gbTileMode; local in function:Addr::V1::SiLib::ReadGbTileMode
3079 gbTileMode.val = regValue;
3081 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
3082 pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
3083 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3084 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
3085 pCfg->info.macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
3086 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
3087 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
3089 UINT_32 regArrayMode = gbTileMode
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