Searched refs:gfx10 (Results 1 - 25 of 34) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A Dgfx10.json1044 "chips": ["gfx10"],
1050 "chips": ["gfx10"],
1056 "chips": ["gfx10"],
1062 "chips": ["gfx10"],
1068 "chips": ["gfx10"],
1074 "chips": ["gfx10"],
1080 "chips": ["gfx10"],
1086 "chips": ["gfx10"],
1091 "chips": ["gfx10"],
1097 "chips": ["gfx10"],
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H A Dpkt3.json132 "chips": ["gfx9", "gfx10", "gfx103"],
144 "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
150 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
168 "chips": ["gfx9", "gfx10", "gfx103"],
174 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
180 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
198 "chips": ["gfx9", "gfx10", "gfx103"],
204 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
209 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
214 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx10
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H A Dgfx10-rsrc.json198 "chips": ["gfx10", "gfx103"],
203 "chips": ["gfx10", "gfx103"],
209 "chips": ["gfx10", "gfx103"],
214 "chips": ["gfx10"],
226 "chips": ["gfx10", "gfx103"],
232 "chips": ["gfx10", "gfx103"],
237 "chips": ["gfx10", "gfx103"],
243 "chips": ["gfx10", "gfx103"],
249 "chips": ["gfx10", "gfx103"],
255 "chips": ["gfx10"],
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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_opcodes.py379 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
380 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
415 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
416 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
493 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
494 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
521 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
522 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
568 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu):
569 opcode(name, gfx7, gfx9, gfx10, Forma
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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.2.0.rst322 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the
325 - radeonsi/gfx10: fix tessellation for the legacy pipeline
326 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy
328 - radeonsi/gfx10: create the GS copy shader if using legacy streamout
329 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
330 - radeonsi/gfx10: fix InstanceID for legacy VS+GS
331 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
332 - radeonsi/gfx10: always use the legacy pipeline for streamout
333 - radeonsi/gfx10: finish up Navi14, add PCI ID
334 - radeonsi/gfx10
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H A D20.2.4.rst108 - radeonsi: disable WGP mode on gfx10.3 to prevent hangs
112 - radeonsi/gfx10: flush gfx cs on ngg -> legacy transition
H A D19.2.7.rst72 - radv/gfx10: fix implementation of exclusive scans
H A D19.2.1.rst122 - radeonsi/gfx10: fix L2 cache rinse programming
126 - radeonsi/gfx10: fix corruption for chips with harvested TCCs
H A D21.1.4.rst155 - aco/gfx10: NGG zero output workaround for conservative rasterization.
156 - aco/gfx10: Emit barrier at the start of NGG VS and TES.
H A D19.3.0.rst2321 - radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the
2324 - radeonsi/gfx10: fix tessellation for the legacy pipeline
2325 - radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy
2327 - radeonsi/gfx10: create the GS copy shader if using legacy streamout
2328 - radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
2329 - radeonsi/gfx10: fix InstanceID for legacy VS+GS
2330 - radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
2331 - radeonsi/gfx10: always use the legacy pipeline for streamout
2332 - radeonsi/gfx10: finish up Navi14, add PCI ID
2333 - radeonsi/gfx10
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H A D19.2.5.rst102 - radeonsi: disable sdma for gfx10
H A D20.1.5.rst114 - radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING
H A D19.3.3.rst149 - ac/gpu_info: always use distributed tessellation on gfx10
202 - aco/gfx10: Fix VcmpxExecWARHazard mitigation.
H A D20.0.3.rst158 - radv/gfx10: fix required subgroup size with
160 - radv/gfx10: fix required ballot size with
H A D20.2.5.rst109 - ac: fix min/max_good_num_cu_per_sa on gfx10.3 with disabled SEs
110 - radeonsi: disable SDMA on gfx6-7 and gfx10.3 to decrease CPU overhead
H A D20.0.0.rst2289 - radeonsi/gfx10: simplify some duplicated NGG GS code
2290 - radeonsi/gfx10: fix the vertex order for triangle strips emitted by a
2311 - radeonsi/gfx10: disable vertex grouping
2312 - radeonsi/gfx10: simplify the tess_turns_off_ngg condition
2321 - radeonsi/gfx10: don't insert NGG streamout atomics if they are never
2327 - radeonsi/gfx10: fix ngg_get_ordered_id
2330 - radeonsi/gfx10: don't declare any LDS for NGG if it's not used
2331 - radeonsi/gfx10: enable NGG passthrough for eligible shaders
2332 - radeonsi/gfx10: improve performance for TES using PrimID but not
2338 gfx10
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H A D19.2.3.rst133 - radv/gfx10: fix 3D images
H A D19.3.2.rst126 - radv/gfx10: fix the out-of-bounds check for vertex descriptors
H A D20.0.2.rst34 - [RadeonSI][gfx10/navi] Kerbal Space Program crash: si_draw_vbo:
H A D20.1.6.rst122 - radv/gfx10: add missing initialization of registers
H A D20.2.2.rst94 - Revert "radeonsi/gfx10: disable vertex grouping"
H A D21.1.2.rst133 - radeonsi: add a gfx10 hw bug workaround with the barrier before gs_alloc_req
H A D21.1.3.rst115 - radeonsi: add a gfx10 bug workaround for NOT_EOP
H A D21.3.4.rst143 - radeonsi/gfx10: fix si_texture_get_offset for mipmapped tex
H A D20.1.0.rst197 - [RadeonSI][gfx10/navi] Kerbal Space Program crash: si_draw_vbo:
3045 - radeonsi/gfx10: cache metadata in L2 on small chips
3046 - radeonsi: set better tessellation tunables on gfx9 and gfx10
3049 - ac: disable late alloc on small gfx10 chips
3115 - radeonsi/gfx10: don't use NGG culling if compute-based culling is
3117 - radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based
3119 - radeonsi/gfx10: user correct ACQUIRE_MEM packet for compute-based
3121 - radeonsi/gfx10: fix the wave size for compute-based culling
3122 - radeonsi/gfx10: fix descriptors and compute registers for
3142 - ac: out-of-order rasterization is not supported on gfx10
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