Searched refs:gfx9 (Results 1 - 25 of 105) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A Dgfx9.json1222 "chips": ["gfx9"],
1228 "chips": ["gfx9"],
1234 "chips": ["gfx9"],
1240 "chips": ["gfx9"],
1246 "chips": ["gfx9"],
1252 "chips": ["gfx9"],
1258 "chips": ["gfx9"],
1264 "chips": ["gfx9"],
1269 "chips": ["gfx9"],
1275 "chips": ["gfx9"],
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H A Dpkt3.json132 "chips": ["gfx9", "gfx10", "gfx103"],
144 "chips": ["gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
150 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
168 "chips": ["gfx9", "gfx10", "gfx103"],
174 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
180 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
198 "chips": ["gfx9", "gfx10", "gfx103"],
204 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
209 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx10", "gfx103"],
214 "chips": ["gfx6", "gfx7", "gfx8", "gfx81", "gfx9", "gfx1
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/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c150 return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
151 surf->u.gfx9.color.dcc.independent_128B_blocks &&
152 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
154 surf->u.gfx9.color.dcc.independent_64B_blocks &&
155 surf->u.gfx9.color.dcc.independent_128B_blocks &&
156 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
185 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
186 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
187 surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
1446 return surf->u.gfx9
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H A Dac_surface_modifier_test.c78 din.swizzleMode = surf->u.gfx9.swizzle_mode;
86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned;
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned;
95 dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode;
128 _mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max,
129 sizeof(surf->u.gfx9.color.display_dcc_pitch_max));
133 input.swizzleMode = surf->u.gfx9.swizzle_mode;
142 input.pitchInElement = surf->u.gfx9.surf_pitch;
148 surf->u.gfx9.color.dcc.rb_aligned,
149 surf->u.gfx9
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/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_meta_dcc_retile.c62 nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
65 &surf->u.gfx9.color.dcc_equation, src_dcc_pitch,
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
172 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
198 unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
234 .range = image->planes[0].surface.u.gfx9.color.display_dcc_size,
265 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
267 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
270 image->planes[0].surface.u.gfx9
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H A Dradv_image.c118 return info->bo_metadata->u.gfx9.scanout;
426 if (md->u.gfx9.swizzle_mode > 0)
431 surface->u.gfx9.swizzle_mode = md->u.gfx9.swizzle_mode;
736 va += plane->surface.u.gfx9.zs.stencil_offset;
738 va += plane->surface.u.gfx9.surf_offset;
774 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode);
776 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode);
788 meta = plane->surface.u.gfx9.color.dcc;
803 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9
838 radv_tex_dim(VkImageType image_type,VkImageViewType view_type,unsigned nr_layers,unsigned nr_samples,bool is_storage_image,bool gfx9) argument
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/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.c1099 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
1100 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1103 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1104 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize;
1108 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
1109 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
1115 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
1116 surf->u.gfx9.fmask.epitch = surf->u.gfx9
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_shaderlib_nir.c83 coord = nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width,
84 surf->u.gfx9.color.dcc_block_height));
87 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation,
95 ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
129 nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width,
130 tex->surface.u.gfx9.color.dcc_block_height,
131 tex->surface.u.gfx9.color.dcc_block_depth, 0), 0x7));
135 &tex->surface.u.gfx9.color.dcc_equation,
H A Dsi_sdma_copy_image.c116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset;
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset;
118 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch;
119 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch;
135 src_address += ssrc->surface.u.gfx9.offset[0];
136 dst_address += sdst->surface.u.gfx9.offset[0];
159 unsigned linear_slice_pitch = ((uint64_t)linear->surface.u.gfx9.surf_slice_size) / bpp;
167 linear_address += linear->surface.u.gfx9.offset[0];
189 tiled->surface.u.gfx9.swizzle_mode << 3 |
190 tiled->surface.u.gfx9
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H A Dsi_compute_blit.c481 ssrc->surface.u.gfx9.color.dcc.pipe_aligned);
485 sdst->surface.u.gfx9.color.dcc.pipe_aligned);
545 info.block[0] = ssrc->surface.u.gfx9.color.dcc_block_width;
546 info.block[1] = ssrc->surface.u.gfx9.color.dcc_block_height;
547 info.block[2] = ssrc->surface.u.gfx9.color.dcc_block_depth;
615 sctx->cs_user_data[1] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) |
616 (tex->surface.u.gfx9.color.dcc_height << 16);
617 sctx->cs_user_data[2] = (tex->surface.u.gfx9.color.display_dcc_pitch_max + 1) |
618 (tex->surface.u.gfx9.color.display_dcc_height << 16);
623 void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9
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H A Dsi_clear.c312 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset;
313 clear_size = tex->surface.u.gfx9.meta_levels[level].size;
379 assert(tex->surface.u.gfx9.swizzle_mode >= 4);
389 assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0);
393 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
394 tex->surface.u.gfx9.swizzle_mode += 2; /* D */
397 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
398 tex->surface.u.gfx9.swizzle_mode += 1; /* S */
401 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
402 tex->surface.u.gfx9
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/xsrc/external/mit/MesaLib.old/dist/src/amd/
H A DMakefile.sources25 addrlib/src/gfx9/gfx9addrlib.cpp \
26 addrlib/src/gfx9/gfx9addrlib.h \
27 addrlib/src/chip/gfx9/gfx9_gb_reg.h \
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.3.2.rst50 - radv/gfx9: add support for 3d images to blit 2d paths
54 - radv/gfx9: add 3d sampler image->buffer copy shader. (v3)
73 - radv/gfx9: fix primitive topology when adjacency is used
H A D17.2.1.rst67 - radv: disable 1d/2d linear optimisation on gfx9.
68 - radv/gfx9: set descriptor up for base_mip to level range.
71 - radv/gfx9: allocate events from uncached VA space
75 - radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
77 - radv/gfx9: fix image resource handling.
84 - cherry-ignore: ignore gfx9 tile swizzle fix
128 - radeonsi/gfx9: always flush DB metadata on framebuffer changes
H A D17.3.3.rst58 - Revert "radv/gfx9: fix block compression texture views."
69 - radv/gfx9: fix 3d image to image transfers on compute queues.
70 - radv/gfx9: fix 3d image clears on compute queues
71 - radv/gfx9: fix buffer to image for 3d images on compute queues
72 - radv/gfx9: fix block compression texture views.
73 - radv/gfx9: use a bigger hammer to flush cb/db caches.
74 - radv/gfx9: use correct swizzle parameter to work out border swizzle.
H A D17.2.5.rst91 - radeon/video: add gfx9 offsets when rejoin the video surface
97 - ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
109 - amd/common/gfx9: workaround DCC corruption more conservatively
H A D17.1.10.rst52 - cherry-ignore: add "radv: gfx9 fixes"
53 - cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d
55 - cherry-ignore: add "radv/gfx9: fix image resource handling."
100 - cherry-ignore: add "ac/surface: handle S8 on gfx9"
H A D17.2.2.rst58 - ac/surface: handle S8 on gfx9
63 - radv: add gfx9 scissor workaround
104 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
H A D17.1.9.rst48 - cherry-ignore: add "radeonsi/gfx9: always flush DB metadata on
52 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_opcodes.py379 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
380 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
415 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
416 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
493 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
494 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
521 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
522 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
568 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu):
569 opcode(name, gfx7, gfx9, gfx1
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_dec_jpeg.c50 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
52 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
53 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
56 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch;
H A Dradeon_video.c176 surfaces[i]->u.gfx9.surf_offset += off;
177 for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
178 surfaces[i]->u.gfx9.offset[j] += off;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_texture.c189 *stride = tex->surface.u.gfx9.surf_pitch * tex->surface.bpe;
190 *layer_stride = tex->surface.u.gfx9.surf_slice_size;
197 return box->z * tex->surface.u.gfx9.surf_slice_size +
198 tex->surface.u.gfx9.offset[level] +
200 tex->surface.u.gfx9.surf_pitch +
320 surface->u.gfx9.surf_pitch = pitch;
321 surface->u.gfx9.surf_slice_size =
322 (uint64_t)pitch * surface->u.gfx9.surf_height * bpe;
324 surface->u.gfx9.surf_offset = offset;
346 if (metadata->u.gfx9
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H A Dsi_clear.c287 assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
297 assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
301 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
302 tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
305 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
306 tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
309 tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
310 tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_image.c360 va += plane->surface.u.gfx9.stencil_offset;
362 va += plane->surface.u.gfx9.surf_offset;
397 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
398 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
400 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
401 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
411 meta = plane->surface.u.gfx9.dcc;
413 meta = plane->surface.u.gfx9.htile;
432 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
438 if (gfx9
431 radv_tex_dim(VkImageType image_type,VkImageViewType view_type,unsigned nr_layers,unsigned nr_samples,bool is_storage_image,bool gfx9) argument
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