Searched refs:hevc_deblock (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A Dradeon_vcn_enc_3_0.c143 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
144 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
150 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
153 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
155 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
156 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
157 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
H A Dradeon_vcn_enc_2_0.c181 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
182 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
195 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
235 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
236 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
237 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
238 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
239 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
240 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
376 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock
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H A Dradeon_uvd_enc_1_1.c358 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
360 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
362 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
363 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
364 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
365 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
368 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
369 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
370 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
371 RADEON_ENC_CS(enc->enc_pic.hevc_deblock
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H A Dradeon_vcn_enc_1_2.c261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
262 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
263 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
264 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
265 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
266 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
688 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
689 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
695 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
698 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock
[all...]
H A Dradeon_vcn_enc.c158 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
160 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
162 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
163 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
164 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
165 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
H A Dradeon_uvd_enc.h377 ruvd_enc_hevc_deblocking_filter_t hevc_deblock; member in struct:radeon_uvd_enc_pic
H A Dradeon_vcn_enc.h468 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; member in struct:radeon_enc_pic
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A Dradeon_uvd_enc_1_1.c402 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
404 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
406 enc->enc_pic.hevc_deblock.beta_offset_div2 =
408 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
409 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
410 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
413 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
414 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
415 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
416 RADEON_ENC_CS(enc->enc_pic.hevc_deblock
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H A Dradeon_vcn_enc_1_2.c443 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled = pic->slice.slice_loop_filter_across_slices_enabled_flag;
444 enc->enc_pic.hevc_deblock.deblocking_filter_disabled = pic->slice.slice_deblocking_filter_disabled_flag;
445 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
446 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
447 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
448 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
451 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
452 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
453 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
454 RADEON_ENC_CS(enc->enc_pic.hevc_deblock
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H A Dradeon_uvd_enc.h413 ruvd_enc_hevc_deblocking_filter_t hevc_deblock; member in struct:radeon_uvd_enc_pic
H A Dradeon_vcn_enc.h437 rvcn_enc_hevc_deblocking_filter_t hevc_deblock; member in struct:radeon_enc_pic

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