Searched refs:instr (Results 1 - 25 of 812) sorted by relevance

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/xsrc/external/mit/MesaLib/src/compiler/nir/
H A Dnir_intrinsics_indices.h30 nir_intrinsic_base(const nir_intrinsic_instr *instr) argument
32 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
34 return (int)instr->const_index[info->index_map[NIR_INTRINSIC_BASE] - 1];
38 nir_intrinsic_set_base(nir_intrinsic_instr *instr, int val) argument
40 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
42 instr->const_index[info->index_map[NIR_INTRINSIC_BASE] - 1] = val;
46 nir_intrinsic_has_base(const nir_intrinsic_instr *instr) argument
48 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
54 nir_intrinsic_write_mask(const nir_intrinsic_instr *instr) argument
56 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr
62 nir_intrinsic_set_write_mask(nir_intrinsic_instr * instr,unsigned val) argument
70 nir_intrinsic_has_write_mask(const nir_intrinsic_instr * instr) argument
78 nir_intrinsic_stream_id(const nir_intrinsic_instr * instr) argument
86 nir_intrinsic_set_stream_id(nir_intrinsic_instr * instr,unsigned val) argument
94 nir_intrinsic_has_stream_id(const nir_intrinsic_instr * instr) argument
102 nir_intrinsic_ucp_id(const nir_intrinsic_instr * instr) argument
110 nir_intrinsic_set_ucp_id(nir_intrinsic_instr * instr,unsigned val) argument
118 nir_intrinsic_has_ucp_id(const nir_intrinsic_instr * instr) argument
126 nir_intrinsic_range_base(const nir_intrinsic_instr * instr) argument
134 nir_intrinsic_set_range_base(nir_intrinsic_instr * instr,unsigned val) argument
142 nir_intrinsic_has_range_base(const nir_intrinsic_instr * instr) argument
150 nir_intrinsic_range(const nir_intrinsic_instr * instr) argument
158 nir_intrinsic_set_range(nir_intrinsic_instr * instr,unsigned val) argument
166 nir_intrinsic_has_range(const nir_intrinsic_instr * instr) argument
174 nir_intrinsic_desc_set(const nir_intrinsic_instr * instr) argument
182 nir_intrinsic_set_desc_set(nir_intrinsic_instr * instr,unsigned val) argument
190 nir_intrinsic_has_desc_set(const nir_intrinsic_instr * instr) argument
198 nir_intrinsic_binding(const nir_intrinsic_instr * instr) argument
206 nir_intrinsic_set_binding(nir_intrinsic_instr * instr,unsigned val) argument
214 nir_intrinsic_has_binding(const nir_intrinsic_instr * instr) argument
222 nir_intrinsic_component(const nir_intrinsic_instr * instr) argument
230 nir_intrinsic_set_component(nir_intrinsic_instr * instr,unsigned val) argument
238 nir_intrinsic_has_component(const nir_intrinsic_instr * instr) argument
246 nir_intrinsic_column(const nir_intrinsic_instr * instr) argument
254 nir_intrinsic_set_column(nir_intrinsic_instr * instr,unsigned val) argument
262 nir_intrinsic_has_column(const nir_intrinsic_instr * instr) argument
270 nir_intrinsic_interp_mode(const nir_intrinsic_instr * instr) argument
278 nir_intrinsic_set_interp_mode(nir_intrinsic_instr * instr,unsigned val) argument
286 nir_intrinsic_has_interp_mode(const nir_intrinsic_instr * instr) argument
294 nir_intrinsic_reduction_op(const nir_intrinsic_instr * instr) argument
302 nir_intrinsic_set_reduction_op(nir_intrinsic_instr * instr,unsigned val) argument
310 nir_intrinsic_has_reduction_op(const nir_intrinsic_instr * instr) argument
318 nir_intrinsic_cluster_size(const nir_intrinsic_instr * instr) argument
326 nir_intrinsic_set_cluster_size(nir_intrinsic_instr * instr,unsigned val) argument
334 nir_intrinsic_has_cluster_size(const nir_intrinsic_instr * instr) argument
342 nir_intrinsic_param_idx(const nir_intrinsic_instr * instr) argument
350 nir_intrinsic_set_param_idx(nir_intrinsic_instr * instr,unsigned val) argument
358 nir_intrinsic_has_param_idx(const nir_intrinsic_instr * instr) argument
366 nir_intrinsic_image_dim(const nir_intrinsic_instr * instr) argument
374 nir_intrinsic_set_image_dim(nir_intrinsic_instr * instr,enum glsl_sampler_dim val) argument
382 nir_intrinsic_has_image_dim(const nir_intrinsic_instr * instr) argument
390 nir_intrinsic_image_array(const nir_intrinsic_instr * instr) argument
398 nir_intrinsic_set_image_array(nir_intrinsic_instr * instr,bool val) argument
406 nir_intrinsic_has_image_array(const nir_intrinsic_instr * instr) argument
414 nir_intrinsic_format(const nir_intrinsic_instr * instr) argument
422 nir_intrinsic_set_format(nir_intrinsic_instr * instr,enum pipe_format val) argument
430 nir_intrinsic_has_format(const nir_intrinsic_instr * instr) argument
438 nir_intrinsic_access(const nir_intrinsic_instr * instr) argument
446 nir_intrinsic_set_access(nir_intrinsic_instr * instr,enum gl_access_qualifier val) argument
454 nir_intrinsic_has_access(const nir_intrinsic_instr * instr) argument
462 nir_intrinsic_call_idx(const nir_intrinsic_instr * instr) argument
470 nir_intrinsic_set_call_idx(nir_intrinsic_instr * instr,unsigned val) argument
478 nir_intrinsic_has_call_idx(const nir_intrinsic_instr * instr) argument
486 nir_intrinsic_stack_size(const nir_intrinsic_instr * instr) argument
494 nir_intrinsic_set_stack_size(nir_intrinsic_instr * instr,unsigned val) argument
502 nir_intrinsic_has_stack_size(const nir_intrinsic_instr * instr) argument
510 nir_intrinsic_align_mul(const nir_intrinsic_instr * instr) argument
518 nir_intrinsic_set_align_mul(nir_intrinsic_instr * instr,unsigned val) argument
526 nir_intrinsic_has_align_mul(const nir_intrinsic_instr * instr) argument
534 nir_intrinsic_align_offset(const nir_intrinsic_instr * instr) argument
542 nir_intrinsic_set_align_offset(nir_intrinsic_instr * instr,unsigned val) argument
550 nir_intrinsic_has_align_offset(const nir_intrinsic_instr * instr) argument
558 nir_intrinsic_desc_type(const nir_intrinsic_instr * instr) argument
566 nir_intrinsic_set_desc_type(nir_intrinsic_instr * instr,unsigned val) argument
574 nir_intrinsic_has_desc_type(const nir_intrinsic_instr * instr) argument
582 nir_intrinsic_src_type(const nir_intrinsic_instr * instr) argument
590 nir_intrinsic_set_src_type(nir_intrinsic_instr * instr,nir_alu_type val) argument
598 nir_intrinsic_has_src_type(const nir_intrinsic_instr * instr) argument
606 nir_intrinsic_dest_type(const nir_intrinsic_instr * instr) argument
614 nir_intrinsic_set_dest_type(nir_intrinsic_instr * instr,nir_alu_type val) argument
622 nir_intrinsic_has_dest_type(const nir_intrinsic_instr * instr) argument
630 nir_intrinsic_swizzle_mask(const nir_intrinsic_instr * instr) argument
638 nir_intrinsic_set_swizzle_mask(nir_intrinsic_instr * instr,unsigned val) argument
646 nir_intrinsic_has_swizzle_mask(const nir_intrinsic_instr * instr) argument
654 nir_intrinsic_is_swizzled(const nir_intrinsic_instr * instr) argument
662 nir_intrinsic_set_is_swizzled(nir_intrinsic_instr * instr,bool val) argument
670 nir_intrinsic_has_is_swizzled(const nir_intrinsic_instr * instr) argument
678 nir_intrinsic_slc_amd(const nir_intrinsic_instr * instr) argument
686 nir_intrinsic_set_slc_amd(nir_intrinsic_instr * instr,bool val) argument
694 nir_intrinsic_has_slc_amd(const nir_intrinsic_instr * instr) argument
702 nir_intrinsic_dst_access(const nir_intrinsic_instr * instr) argument
710 nir_intrinsic_set_dst_access(nir_intrinsic_instr * instr,enum gl_access_qualifier val) argument
718 nir_intrinsic_has_dst_access(const nir_intrinsic_instr * instr) argument
726 nir_intrinsic_src_access(const nir_intrinsic_instr * instr) argument
734 nir_intrinsic_set_src_access(nir_intrinsic_instr * instr,enum gl_access_qualifier val) argument
742 nir_intrinsic_has_src_access(const nir_intrinsic_instr * instr) argument
750 nir_intrinsic_driver_location(const nir_intrinsic_instr * instr) argument
758 nir_intrinsic_set_driver_location(nir_intrinsic_instr * instr,unsigned val) argument
766 nir_intrinsic_has_driver_location(const nir_intrinsic_instr * instr) argument
774 nir_intrinsic_memory_semantics(const nir_intrinsic_instr * instr) argument
782 nir_intrinsic_set_memory_semantics(nir_intrinsic_instr * instr,nir_memory_semantics val) argument
790 nir_intrinsic_has_memory_semantics(const nir_intrinsic_instr * instr) argument
798 nir_intrinsic_memory_modes(const nir_intrinsic_instr * instr) argument
806 nir_intrinsic_set_memory_modes(nir_intrinsic_instr * instr,nir_variable_mode val) argument
814 nir_intrinsic_has_memory_modes(const nir_intrinsic_instr * instr) argument
822 nir_intrinsic_memory_scope(const nir_intrinsic_instr * instr) argument
830 nir_intrinsic_set_memory_scope(nir_intrinsic_instr * instr,nir_scope val) argument
838 nir_intrinsic_has_memory_scope(const nir_intrinsic_instr * instr) argument
846 nir_intrinsic_execution_scope(const nir_intrinsic_instr * instr) argument
854 nir_intrinsic_set_execution_scope(nir_intrinsic_instr * instr,nir_scope val) argument
862 nir_intrinsic_has_execution_scope(const nir_intrinsic_instr * instr) argument
870 nir_intrinsic_io_semantics(const nir_intrinsic_instr * instr) argument
881 nir_intrinsic_set_io_semantics(nir_intrinsic_instr * instr,struct nir_io_semantics val) argument
891 nir_intrinsic_has_io_semantics(const nir_intrinsic_instr * instr) argument
899 nir_intrinsic_rounding_mode(const nir_intrinsic_instr * instr) argument
907 nir_intrinsic_set_rounding_mode(nir_intrinsic_instr * instr,nir_rounding_mode val) argument
915 nir_intrinsic_has_rounding_mode(const nir_intrinsic_instr * instr) argument
923 nir_intrinsic_saturate(const nir_intrinsic_instr * instr) argument
931 nir_intrinsic_set_saturate(nir_intrinsic_instr * instr,unsigned val) argument
939 nir_intrinsic_has_saturate(const nir_intrinsic_instr * instr) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
H A Dsfn_emitaluinstruction.h52 bool do_emit(nir_instr* instr) override;
54 void split_constants(const nir_alu_instr& instr, unsigned nsrc_comp);
56 bool emit_mov(const nir_alu_instr& instr);
57 bool emit_alu_op1(const nir_alu_instr& instr, EAluOp opcode, const AluOpFlags &flags = 0);
58 bool emit_alu_op2(const nir_alu_instr& instr, EAluOp opcode, AluOp2Opts ops = op2_opt_none);
60 bool emit_alu_trans_op2(const nir_alu_instr& instr, EAluOp opcode);
61 bool emit_alu_cm_trig(const nir_alu_instr& instr, EAluOp opcode);
63 bool emit_alu_inot(const nir_alu_instr& instr);
64 bool emit_alu_ineg(const nir_alu_instr& instr);
65 bool emit_alu_op2_int(const nir_alu_instr& instr, EAluO
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H A Dsfn_emitaluinstruction.cpp45 const nir_alu_instr& instr = *nir_instr_as_alu(ir); local in function:r600::EmitAluInstruction::do_emit
47 r600::sfn_log << SfnLog::instr << "emit '"
49 << " bitsize: " << static_cast<int>(instr.dest.dest.ssa.bit_size)
52 preload_src(instr);
55 switch (instr.op) {
56 case nir_op_fcos_r600: return emit_alu_cm_trig(instr, op1_cos);
57 case nir_op_fexp2: return emit_alu_cm_trig(instr, op1_exp_ieee);
58 case nir_op_flog2: return emit_alu_cm_trig(instr, op1_log_clamped);
59 case nir_op_frcp: return emit_alu_cm_trig(instr, op1_recip_ieee);
60 case nir_op_frsq: return emit_alu_cm_trig(instr, op1_recipsqrt_ieee
213 preload_src(const nir_alu_instr & instr) argument
236 num_src_comp(const nir_alu_instr & instr) argument
286 emit_cube(const nir_alu_instr & instr) argument
302 split_constants(const nir_alu_instr & instr,unsigned nsrc_comp) argument
346 emit_alu_inot(const nir_alu_instr & instr) argument
365 emit_alu_op1(const nir_alu_instr & instr,EAluOp opcode,const AluOpFlags & flags) argument
391 emit_mov(const nir_alu_instr & instr) argument
410 emit_alu_trans_op1(const nir_alu_instr & instr,EAluOp opcode,bool absolute) argument
445 emit_alu_cm_trig(const nir_alu_instr & instr,EAluOp opcode) argument
470 emit_alu_f2i32_or_u32(const nir_alu_instr & instr,EAluOp op) argument
514 emit_alu_f2b32(const nir_alu_instr & instr) argument
528 emit_b2i32(const nir_alu_instr & instr) argument
544 emit_pack_64_2x32_split(const nir_alu_instr & instr) argument
558 emit_unpack_64_2x32_split(const nir_alu_instr & instr,unsigned comp) argument
565 emit_create_vec(const nir_alu_instr & instr,unsigned nc) argument
592 emit_dot(const nir_alu_instr & instr,int n) argument
623 emit_fdph(const nir_alu_instr & instr) argument
652 emit_alu_i2orf2_b1(const nir_alu_instr & instr,EAluOp op) argument
668 emit_alu_b2f(const nir_alu_instr & instr) argument
686 emit_any_all_icomp(const nir_alu_instr & instr,EAluOp op,unsigned nc,bool all) argument
727 emit_any_all_fcomp(const nir_alu_instr & instr,EAluOp op,unsigned nc,bool all) argument
782 emit_any_all_fcomp2(const nir_alu_instr & instr,EAluOp op,bool all) argument
813 emit_alu_trans_op2(const nir_alu_instr & instr,EAluOp opcode) argument
852 emit_alu_op2_int(const nir_alu_instr & instr,EAluOp opcode,AluOp2Opts opts) argument
866 emit_alu_op2(const nir_alu_instr & instr,EAluOp opcode,AluOp2Opts ops) argument
899 emit_alu_op3(const nir_alu_instr & instr,EAluOp opcode,std::array<uint8_t,3> reorder) argument
929 emit_alu_ineg(const nir_alu_instr & instr) argument
963 emit_tex_fdd(const nir_alu_instr & instr,TexInstruction::Opcode op,bool fine) argument
1004 emit_unpack_32_2x16_split_y(const nir_alu_instr & instr) argument
1017 emit_unpack_32_2x16_split_x(const nir_alu_instr & instr) argument
1024 emit_pack_32_2x16_split(const nir_alu_instr & instr) argument
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/gp/
H A Ddisasm.c50 print_dest(gpir_codegen_instr *instr, gp_unit unit, unsigned cur_dest_index) argument
56 if (instr->store0_src_x == src ||
57 instr->store0_src_y == src) {
58 if (instr->store0_temporary) {
64 if (instr->store0_varying)
68 printf("%u", instr->store0_addr);
72 if (instr->store0_src_x == src)
74 if (instr->store0_src_y == src)
78 if (instr->store1_src_z == src ||
79 instr
118 print_src(gpir_codegen_src src,gp_unit unit,unsigned unit_src_num,gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned cur_dest_index) argument
247 print_mul(gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned cur_dest_index) argument
382 print_acc(gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned cur_dest_index) argument
453 print_pass(gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned cur_dest_index) argument
494 print_complex(gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned cur_dest_index) argument
535 print_instr(gpir_codegen_instr * instr,gpir_codegen_instr * prev_instr,unsigned instr_number,unsigned cur_dest_index) argument
563 for (gpir_codegen_instr *instr = code; cur_instr < num_instr; local in function:gpir_disassemble_program
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H A Dinstr.c33 gpir_instr *instr = rzalloc(block, gpir_instr); local in function:gpir_instr_create
34 if (unlikely(!instr))
37 instr->index = block->sched.instr_index++;
38 instr->alu_num_slot_free = 6;
40 list_add(&instr->list, &block->instr_list);
41 return instr;
44 static gpir_node *gpir_instr_get_the_other_acc_node(gpir_instr *instr, int slot) argument
47 return instr->slots[GPIR_INSTR_SLOT_ADD1];
49 return instr->slots[GPIR_INSTR_SLOT_ADD0];
54 static bool gpir_instr_check_acc_same_op(gpir_instr *instr, gpir_nod argument
67 gpir_instr_get_consume_slot(gpir_instr * instr,gpir_node * node) argument
82 gpir_instr_insert_alu_check(gpir_instr * instr,gpir_node * node) argument
118 gpir_instr_remove_alu(gpir_instr * instr,gpir_node * node) argument
134 gpir_instr_insert_reg0_check(gpir_instr * instr,gpir_node * node) argument
158 gpir_instr_remove_reg0(gpir_instr * instr,gpir_node * node) argument
165 gpir_instr_insert_reg1_check(gpir_instr * instr,gpir_node * node) argument
184 gpir_instr_remove_reg1(gpir_instr * instr,gpir_node * node) argument
189 gpir_instr_insert_mem_check(gpir_instr * instr,gpir_node * node) argument
213 gpir_instr_remove_mem(gpir_instr * instr,gpir_node * node) argument
220 gpir_instr_insert_store_check(gpir_instr * instr,gpir_node * node) argument
295 gpir_instr_remove_store(gpir_instr * instr,gpir_node * node) argument
319 gpir_instr_spill_move(gpir_instr * instr,int slot,int spill_to_start) argument
344 gpir_instr_slot_free(gpir_instr * instr,gpir_node * node) argument
370 gpir_instr_try_insert_node(gpir_instr * instr,gpir_node * node) argument
409 gpir_instr_remove_node(gpir_instr * instr,gpir_node * node) argument
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/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dv3d_nir_lower_scratch.c38 v3d_nir_scratch_offset(nir_builder *b, nir_intrinsic_instr *instr) argument
40 bool is_store = instr->intrinsic == nir_intrinsic_store_scratch;
41 nir_ssa_def *offset = nir_ssa_for_src(b, instr->src[is_store ? 1 : 0], 1);
43 assert(nir_intrinsic_align_mul(instr) >= 4);
44 assert(nir_intrinsic_align_offset(instr) == 0);
54 v3d_nir_lower_load_scratch(nir_builder *b, nir_intrinsic_instr *instr) argument
56 b->cursor = nir_before_instr(&instr->instr);
58 nir_ssa_def *offset = v3d_nir_scratch_offset(b,instr);
61 for (int i = 0; i < instr
86 v3d_nir_lower_store_scratch(nir_builder * b,nir_intrinsic_instr * instr) argument
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/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dv3d_nir_lower_scratch.c38 v3d_nir_scratch_offset(nir_builder *b, nir_intrinsic_instr *instr) argument
40 bool is_store = instr->intrinsic == nir_intrinsic_store_scratch;
41 nir_ssa_def *offset = nir_ssa_for_src(b, instr->src[is_store ? 1 : 0], 1);
43 assert(nir_intrinsic_align_mul(instr) >= 4);
44 assert(nir_intrinsic_align_offset(instr) == 0);
54 v3d_nir_lower_load_scratch(nir_builder *b, nir_intrinsic_instr *instr) argument
56 b->cursor = nir_before_instr(&instr->instr);
58 nir_ssa_def *offset = v3d_nir_scratch_offset(b,instr);
61 for (int i = 0; i < instr
86 v3d_nir_lower_store_scratch(nir_builder * b,nir_intrinsic_instr * instr) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/
H A Dnir_lower_dynamic_bo_access.c45 recursive_generate_bo_ssa_def(nir_builder *b, nir_intrinsic_instr *instr, nir_ssa_def *index, unsigned start, unsigned end) argument
48 nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(b->shader, instr->intrinsic);
50 for (unsigned i = 0; i < nir_intrinsic_infos[instr->intrinsic].num_srcs; i++) {
52 nir_src_copy(&new_instr->src[i], &instr->src[i]);
54 if (instr->intrinsic != nir_intrinsic_load_ubo_vec4) {
55 nir_intrinsic_set_align(new_instr, nir_intrinsic_align_mul(instr), nir_intrinsic_align_offset(instr));
56 if (instr->intrinsic != nir_intrinsic_load_ssbo)
57 nir_intrinsic_set_range(new_instr, nir_intrinsic_range(instr));
59 new_instr->num_components = instr
76 generate_store_ssbo_ssa_def(nir_builder * b,nir_intrinsic_instr * instr,nir_ssa_def * index,unsigned start,unsigned end) argument
101 nir_intrinsic_instr *instr = nir_instr_as_intrinsic(instr_); local in function:lower_dynamic_bo_access_instr
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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_gs_nir.cpp34 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) argument
39 switch (instr->intrinsic) {
41 assert(nir_dest_bit_size(instr->dest) == 32);
45 const unsigned vertex = nir_src_as_uint(instr->src[0]);
46 const unsigned offset_reg = nir_src_as_uint(instr->src[1]);
51 const glsl_type *const type = glsl_type::ivec(instr->num_components);
54 instr->const_index[0] + offset_reg,
56 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
58 dest = get_nir_dest(instr->dest, src.type);
59 dest.writemask = brw_writemask_for_size(instr
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/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir_lower_uniforms_to_ubo.c42 lower_instr(nir_intrinsic_instr *instr, nir_builder *b, int multiplier) argument
44 b->cursor = nir_before_instr(&instr->instr);
46 if (instr->intrinsic == nir_intrinsic_load_ubo) {
47 nir_ssa_def *old_idx = nir_ssa_for_src(b, instr->src[0], 1);
49 nir_instr_rewrite_src(&instr->instr, &instr->src[0],
54 if (instr->intrinsic == nir_intrinsic_load_uniform) {
57 nir_iadd(b, nir_imm_int(b, multiplier * nir_intrinsic_base(instr)),
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H A Dnir_opt_constant_folding.c42 constant_fold_alu_instr(nir_alu_instr *instr, void *mem_ctx) argument
46 if (!instr->dest.dest.is_ssa)
59 if (!nir_alu_type_get_type_size(nir_op_infos[instr->op].output_type))
60 bit_size = instr->dest.dest.ssa.bit_size;
62 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
63 if (!instr->src[i].src.is_ssa)
67 !nir_alu_type_get_type_size(nir_op_infos[instr->op].input_types[i]))
68 bit_size = instr->src[i].src.ssa->bit_size;
70 nir_instr *src_instr = instr->src[i].src.ssa->parent_instr;
76 for (unsigned j = 0; j < nir_ssa_alu_instr_src_components(instr,
118 constant_fold_intrinsic_instr(nir_intrinsic_instr * instr) argument
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H A Dnir_opt_shrink_load.c27 opt_shrink_load(nir_intrinsic_instr *instr) argument
31 if (instr->intrinsic == nir_intrinsic_load_push_constant) {
32 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
34 if (instr->num_components > util_last_bit(mask)) {
35 instr->num_components = util_last_bit(mask);
36 instr->dest.ssa.num_components = instr->num_components;
54 nir_foreach_instr(instr, block) {
55 if (instr->type != nir_instr_type_intrinsic)
58 progress |= opt_shrink_load(nir_instr_as_intrinsic(instr));
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H A Dnir_move_load_const.c54 nir_instr *instr = use->parent_instr; local in function:get_preferred_block
55 nir_block *use_block = instr->block;
64 if (instr->type == nir_instr_type_phi) {
65 nir_phi_instr *phi = nir_instr_as_phi(instr);
80 insert_after_phi(nir_instr *instr, nir_block *block) argument
87 &instr->node);
95 exec_list_push_tail(&block->instr_list, &instr->node);
111 nir_foreach_instr_safe(instr, block) {
112 if (instr->type != nir_instr_type_load_const)
116 nir_instr_as_load_const(instr);
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a2xx/
H A Dir2.c29 static bool scalar_possible(struct ir2_instr *instr) argument
31 if (instr->alu.scalar_opc == SCALAR_NONE)
34 return src_ncomp(instr) == 1;
56 static unsigned alu_vector_prio(struct ir2_instr *instr) argument
58 if (instr->alu.vector_opc == VECTOR_NONE)
61 if (is_export(instr))
65 if (instr->src_count == 3)
68 if (!scalar_possible(instr))
71 return instr->src_count == 2 ? 2 : 3;
75 static unsigned alu_scalar_prio(struct ir2_instr *instr) argument
147 scalarize_case1(struct ir2_context * ctx,struct ir2_instr * instr,bool order) argument
384 struct ir2_instr *instr = sched->instr, *tex_lod; local in function:schedule_instrs
[all...]
H A Dir2_nir_lower_scalar.c36 nir_alu_ssa_dest_init(nir_alu_instr * instr, unsigned num_components, argument
39 nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
41 instr->dest.write_mask = (1 << num_components) - 1;
45 lower_reduction(nir_alu_instr * instr, nir_op chan_op, nir_op merge_op, argument
48 unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
54 nir_alu_ssa_dest_init(chan, 1, instr->dest.dest.ssa.bit_size);
55 nir_alu_src_copy(&chan->src[0], &instr->src[0], chan);
59 nir_alu_src_copy(&chan->src[1], &instr
79 lower_scalar(nir_alu_instr * instr,nir_builder * b) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_gs_nir.cpp34 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) argument
39 switch (instr->intrinsic) {
44 const unsigned vertex = nir_src_as_uint(instr->src[0]);
45 const unsigned offset_reg = nir_src_as_uint(instr->src[1]);
49 if (nir_dest_bit_size(instr->dest) == 64) {
51 instr->const_index[0] + offset_reg,
58 src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr) / 2);
61 dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
62 dest.writemask = brw_writemask_for_size(instr->num_components);
66 const glsl_type *const type = glsl_type::ivec(instr
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_dce.c37 mark_array_use(struct ir3_instruction *instr, struct ir3_register *reg) argument
41 ir3_lookup_array(instr->block->shader, reg->array.id);
47 instr_dce(struct ir3_instruction *instr, bool falsedep) argument
51 instr->flags &= ~IR3_INSTR_UNUSED;
53 if (ir3_instr_check_mark(instr))
56 if (writes_gpr(instr))
57 mark_array_use(instr, instr->dsts[0]); /* dst */
59 foreach_src (reg, instr)
60 mark_array_use(instr, re
162 struct ir3_instruction *instr = ir->a0_users[i]; local in function:find_and_remove_unused
168 struct ir3_instruction *instr = ir->a1_users[i]; local in function:find_and_remove_unused
174 struct ir3_instruction *instr = ir->predicates[i]; local in function:find_and_remove_unused
[all...]
H A Dir3_validate.c72 validate_src(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr, argument
76 validate_assert(ctx, ir3_valid_immediate(instr, reg->iim_val));
83 validate_assert(ctx, _mesa_set_search(ctx->defs, src->instr));
90 foreach_dst (dst, instr) {
130 validate_dst(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr, argument
142 foreach_src (src, instr) {
153 validate_assert(ctx, reg->instr == instr);
156 validate_assert(ctx, instr->address);
164 validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr) argument
[all...]
H A Dir3_print.c70 print_instr_name(struct log_stream *stream, struct ir3_instruction *instr, argument
73 if (!instr)
76 mesa_log_stream_printf(stream, "%04u:", instr->serialno);
78 mesa_log_stream_printf(stream, "%04u:", instr->ip);
79 if (instr->flags & IR3_INSTR_UNUSED) {
82 mesa_log_stream_printf(stream, "%03u: ", instr->use_count);
87 if (instr->flags & IR3_INSTR_SY)
89 if (instr->flags & IR3_INSTR_SS)
91 if (instr->flags & IR3_INSTR_JP)
93 if (instr
228 print_reg_name(struct log_stream * stream,struct ir3_instruction * instr,struct ir3_register * reg,bool dest) argument
304 print_instr(struct log_stream * stream,struct ir3_instruction * instr,int lvl) argument
422 ir3_print_instr_stream(struct log_stream * stream,struct ir3_instruction * instr) argument
428 ir3_print_instr(struct ir3_instruction * instr) argument
[all...]
/xsrc/external/mit/MesaLib/dist/src/broadcom/qpu/
H A Dqpu_disasm.c60 const struct v3d_qpu_instr *instr, uint8_t mux)
63 append(disasm, "rf%d", instr->raddr_a);
65 if (instr->sig.small_imm) {
69 instr->raddr_b,
78 append(disasm, "rf%d", instr->raddr_b);
102 const struct v3d_qpu_instr *instr)
104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op);
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op);
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op));
108 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr
59 v3d_qpu_disasm_raddr(struct disasm_state * disasm,const struct v3d_qpu_instr * instr,uint8_t mux) argument
101 v3d_qpu_disasm_add(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
138 v3d_qpu_disasm_mul(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
181 v3d_qpu_disasm_sig_addr(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
201 v3d_qpu_disasm_sig(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
259 v3d_qpu_disasm_alu(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
268 v3d_qpu_disasm_branch(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
317 v3d_qpu_decode(const struct v3d_device_info * devinfo,const struct v3d_qpu_instr * instr) argument
347 struct v3d_qpu_instr instr; local in function:v3d_qpu_disasm
355 v3d_qpu_dump(const struct v3d_device_info * devinfo,const struct v3d_qpu_instr * instr) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/qpu/
H A Dqpu_disasm.c60 const struct v3d_qpu_instr *instr, uint8_t mux)
63 append(disasm, "rf%d", instr->raddr_a);
65 if (instr->sig.small_imm) {
69 instr->raddr_b,
78 append(disasm, "rf%d", instr->raddr_b);
102 const struct v3d_qpu_instr *instr)
104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op);
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op);
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op));
108 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr
59 v3d_qpu_disasm_raddr(struct disasm_state * disasm,const struct v3d_qpu_instr * instr,uint8_t mux) argument
101 v3d_qpu_disasm_add(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
138 v3d_qpu_disasm_mul(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
181 v3d_qpu_disasm_sig_addr(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
199 v3d_qpu_disasm_sig(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
255 v3d_qpu_disasm_alu(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
264 v3d_qpu_disasm_branch(struct disasm_state * disasm,const struct v3d_qpu_instr * instr) argument
313 v3d_qpu_decode(const struct v3d_device_info * devinfo,const struct v3d_qpu_instr * instr) argument
343 struct v3d_qpu_instr instr; local in function:v3d_qpu_disasm
351 v3d_qpu_dump(const struct v3d_device_info * devinfo,const struct v3d_qpu_instr * instr) argument
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_group.c34 * (where we have a simple instr[] array), and fanin nodes (where we have
35 * an extra indirection via reg->instr).
39 void (*insert_mov)(void *arr, int idx, struct ir3_instruction *instr);
46 static void arr_insert_mov_out(void *arr, int idx, struct ir3_instruction *instr) argument
49 ir3_MOV(instr->block, instr, TYPE_F32);
51 static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr) argument
54 * instruction already has a pointer to 'instr'. So we cheat a bit and
60 debug_assert(instr->regs_count == 1);
62 in = ir3_instr_create(instr
82 instr_insert_mov(void * arr,int idx,struct ir3_instruction * instr) argument
91 in_neighbor_list(struct ir3_instruction * instr,struct ir3_instruction * cur,int pos) argument
122 struct ir3_instruction *instr = ops->get(arr, i); local in function:group_n
160 struct ir3_instruction *instr = ops->get(arr, i); local in function:group_n
181 instr_find_neighbors(struct ir3_instruction * instr) argument
207 struct ir3_instruction *instr = input[i]; local in function:pad_and_group_input
252 struct ir3_instruction *instr = ir->outputs[i]; local in function:find_neighbors
259 struct ir3_instruction *instr = block->keeps[i]; local in function:find_neighbors
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_validate.cpp84 aco::Instruction* instr) -> void
94 aco_print_instr(instr, memf);
114 for (aco_ptr<Instruction>& instr : block.instructions) {
117 Format base_format = instr->format;
127 if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
128 instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
129 instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
130 instr->opcode == aco_opcode::v_interp_p2_f16) {
139 check(base_format == instr_info.format[(int)instr->opcode],
140 "Wrong base format for instruction", instr
676 Instruction* instr; // NULL if it's the block's live-in member in struct:aco::__anon7dcd92540310::Location
721 validate_subdword_operand(chip_class chip,const aco_ptr<Instruction> & instr,unsigned index) argument
778 validate_subdword_definition(chip_class chip,const aco_ptr<Instruction> & instr) argument
809 get_subdword_bytes_written(Program * program,const aco_ptr<Instruction> & instr,unsigned index) argument
969 aco_ptr<Instruction>& instr = *it; local in function:aco::validate_ra
[all...]
/xsrc/external/mit/MesaLib/dist/src/freedreno/isa/
H A Dencode.c28 #include "ir3/instr-a3xx.h" // TODO move opc's and other useful things to ir3-instr.h or so
40 struct ir3_instruction *instr; member in struct:encode_state
49 extract_SRC1_R(struct ir3_instruction *instr) argument
51 if (instr->nop) {
52 assert(!instr->repeat);
53 return instr->nop & 0x1;
55 return !!(instr->srcs[0]->flags & IR3_REG_R);
59 extract_SRC2_R(struct ir3_instruction *instr) argument
61 if (instr
72 __instruction_case(struct encode_state * s,struct ir3_instruction * instr) argument
155 extract_cat5_SRC(struct ir3_instruction * instr,unsigned n) argument
166 extract_cat5_FULL(struct ir3_instruction * instr) argument
176 extract_cat5_DESC_MODE(struct ir3_instruction * instr) argument
212 extract_cat6_DESC_MODE(struct ir3_instruction * instr) argument
232 extract_cat6_SRC(struct ir3_instruction * instr,unsigned n) argument
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/gp/
H A Dinstr.c33 gpir_instr *instr = rzalloc(block, gpir_instr); local in function:gpir_instr_create
34 if (unlikely(!instr))
43 instr->index = block->sched.instr_index++;
44 instr->alu_num_slot_free = 6;
45 instr->alu_non_cplx_slot_free = 5;
46 instr->alu_max_allowed_next_max = 5;
48 list_add(&instr->list, &block->instr_list);
49 return instr;
52 static gpir_node *gpir_instr_get_the_other_acc_node(gpir_instr *instr, int slot) argument
55 return instr
62 gpir_instr_check_acc_same_op(gpir_instr * instr,gpir_node * node,int slot) argument
75 gpir_instr_get_consume_slot(gpir_instr * instr,gpir_node * node) argument
90 gpir_instr_insert_alu_check(gpir_instr * instr,gpir_node * node) argument
159 gpir_instr_remove_alu(gpir_instr * instr,gpir_node * node) argument
184 gpir_instr_insert_reg0_check(gpir_instr * instr,gpir_node * node) argument
208 gpir_instr_remove_reg0(gpir_instr * instr,gpir_node * node) argument
215 gpir_instr_insert_reg1_check(gpir_instr * instr,gpir_node * node) argument
234 gpir_instr_remove_reg1(gpir_instr * instr,gpir_node * node) argument
239 gpir_instr_insert_mem_check(gpir_instr * instr,gpir_node * node) argument
263 gpir_instr_remove_mem(gpir_instr * instr,gpir_node * node) argument
270 gpir_instr_insert_store_check(gpir_instr * instr,gpir_node * node) argument
370 gpir_instr_remove_store(gpir_instr * instr,gpir_node * node) argument
402 gpir_instr_spill_move(gpir_instr * instr,int slot,int spill_to_start) argument
427 gpir_instr_slot_free(gpir_instr * instr,gpir_node * node) argument
453 gpir_instr_try_insert_node(gpir_instr * instr,gpir_node * node) argument
495 gpir_instr_remove_node(gpir_instr * instr,gpir_node * node) argument
[all...]

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