Searched refs:ir2_context (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a2xx/
H A Dir2_ra.c55 static void set_need_emit(struct ir2_context *ctx, struct ir2_instr *instr)
84 static unsigned reg_mask(struct ir2_context *ctx, unsigned idx)
89 static void reg_setmask(struct ir2_context *ctx, unsigned idx, unsigned c)
95 static void reg_freemask(struct ir2_context *ctx, unsigned idx, unsigned c)
101 void ra_count_refs(struct ir2_context *ctx)
132 void ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx,
188 void ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr)
211 void ra_block_free(struct ir2_context *ctx, unsigned block)
H A Dir2_private.h147 struct ir2_context { struct
188 void assemble(struct ir2_context *ctx, bool binning);
190 void ir2_nir_compile(struct ir2_context *ctx, bool binning);
193 void ra_count_refs(struct ir2_context *ctx);
194 void ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx,
196 void ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr);
197 void ra_block_free(struct ir2_context *ctx, unsigned block);
199 void cp_src(struct ir2_context *ctx);
200 void cp_export(struct ir2_context *ctx);
238 struct ir2_src ir2_zero(struct ir2_context *ct
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H A Dir2_nir.c136 load_const(struct ir2_context *ctx, float *value_f, unsigned ncomp)
188 ir2_zero(struct ir2_context *ctx)
194 update_range(struct ir2_context *ctx, struct ir2_reg *reg)
216 make_src(struct ir2_context *ctx, nir_src src)
246 set_index(struct ir2_context *ctx, nir_dest * dst,
264 ir2_instr_create(struct ir2_context *ctx, int type)
278 instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
341 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode,
359 instr_create_alu_dest(struct ir2_context *ctx, nir_op opcode, nir_dest *dst)
368 ir2_instr_create_fetch(struct ir2_context *ct
[all...]
H A Dir2_assemble.c30 src_swizzle(struct ir2_context *ctx, struct ir2_src *src, unsigned ncomp)
55 alu_swizzle_scalar(struct ir2_context *ctx, struct ir2_src *reg)
62 alu_swizzle(struct ir2_context *ctx, struct ir2_instr *instr, struct ir2_src *src)
92 alu_swizzle_scalar2(struct ir2_context *ctx, struct ir2_src *src, unsigned s1)
102 alu_write_mask(struct ir2_context *ctx, struct ir2_instr *instr)
118 fetch_swizzle(struct ir2_context *ctx, struct ir2_src *src, unsigned ncomp)
128 fetch_dst_swiz(struct ir2_context *ctx, struct ir2_instr *instr)
141 dst_to_reg(struct ir2_context *ctx, struct ir2_instr *instr)
150 static unsigned src_to_reg(struct ir2_context *ctx, struct ir2_src *src)
155 static unsigned src_reg_byte(struct ir2_context *ct
[all...]
H A Dir2.c101 insert(struct ir2_context *ctx, unsigned block_idx, unsigned reg_idx,
147 scalarize_case1(struct ir2_context *ctx, struct ir2_instr *instr, bool order)
207 static int sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
363 static void schedule_instrs(struct ir2_context *ctx)
414 struct ir2_context ctx = { };
H A Dir2_cp.c52 void cp_src(struct ir2_context *ctx)
94 void cp_export(struct ir2_context *ctx)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a2xx/
H A Dir2_ra.c57 set_need_emit(struct ir2_context *ctx, struct ir2_instr *instr)
88 reg_mask(struct ir2_context *ctx, unsigned idx)
94 reg_setmask(struct ir2_context *ctx, unsigned idx, unsigned c)
101 reg_freemask(struct ir2_context *ctx, unsigned idx, unsigned c)
108 ra_count_refs(struct ir2_context *ctx)
140 ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx, bool export,
197 ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr)
221 ra_block_free(struct ir2_context *ctx, unsigned block)
H A Dir2_private.h147 struct ir2_context { struct
188 void assemble(struct ir2_context *ctx, bool binning);
190 void ir2_nir_compile(struct ir2_context *ctx, bool binning);
193 void ra_count_refs(struct ir2_context *ctx);
194 void ra_reg(struct ir2_context *ctx, struct ir2_reg *reg, int force_idx,
196 void ra_src_free(struct ir2_context *ctx, struct ir2_instr *instr);
197 void ra_block_free(struct ir2_context *ctx, unsigned block);
199 void cp_src(struct ir2_context *ctx);
200 void cp_export(struct ir2_context *ctx);
235 struct ir2_src ir2_zero(struct ir2_context *ct
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H A Dir2_nir.c148 load_const(struct ir2_context *ctx, float *value_f, unsigned ncomp)
200 ir2_zero(struct ir2_context *ctx)
206 update_range(struct ir2_context *ctx, struct ir2_reg *reg)
228 make_src(struct ir2_context *ctx, nir_src src)
258 set_index(struct ir2_context *ctx, nir_dest *dst, struct ir2_instr *instr)
275 ir2_instr_create(struct ir2_context *ctx, int type)
289 instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
348 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode, uint8_t write_mask,
365 instr_create_alu_dest(struct ir2_context *ctx, nir_op opcode, nir_dest *dst)
374 ir2_instr_create_fetch(struct ir2_context *ct
[all...]
H A Dir2_assemble.c30 src_swizzle(struct ir2_context *ctx, struct ir2_src *src, unsigned ncomp)
55 alu_swizzle_scalar(struct ir2_context *ctx, struct ir2_src *reg)
62 alu_swizzle(struct ir2_context *ctx, struct ir2_instr *instr,
93 alu_swizzle_scalar2(struct ir2_context *ctx, struct ir2_src *src, unsigned s1)
103 alu_write_mask(struct ir2_context *ctx, struct ir2_instr *instr)
119 fetch_swizzle(struct ir2_context *ctx, struct ir2_src *src, unsigned ncomp)
129 fetch_dst_swiz(struct ir2_context *ctx, struct ir2_instr *instr)
142 dst_to_reg(struct ir2_context *ctx, struct ir2_instr *instr)
152 src_to_reg(struct ir2_context *ctx, struct ir2_src *src)
158 src_reg_byte(struct ir2_context *ct
[all...]
H A Dir2_cp.c55 cp_src(struct ir2_context *ctx)
101 cp_export(struct ir2_context *ctx)
H A Dir2.c105 insert(struct ir2_context *ctx, unsigned block_idx, unsigned reg_idx,
157 scalarize_case1(struct ir2_context *ctx, struct ir2_instr *instr, bool order)
218 sched_next(struct ir2_context *ctx, struct ir2_sched_instr *sched)
393 schedule_instrs(struct ir2_context *ctx)
444 struct ir2_context ctx = {};

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